From: "Laurent Desnogues" <laurent.desnogues@gmail.com>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] ARM: fix CPS instruction
Date: Thu, 12 Jun 2008 21:58:53 +0200 [thread overview]
Message-ID: <761ea48b0806121258k28e712a9o7148e6f137db4c2e@mail.gmail.com> (raw)
In-Reply-To: <200806122117.54077.vincent.palatin_qemu@polytechnique.org>
On Thu, Jun 12, 2008 at 9:17 PM, Vincent Palatin
<vincent.palatin_qemu@polytechnique.org> wrote:
> I attach a patch with 2 fixes for the ARMv6 instruction "CPS".
> According to ARM Reference Manual (DDI0100 A4.1.16),
> bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
> should be 0x0ff10020 not 0x0ff10010.
> Besides, mmod flag is bit 17 (b14 is SBZ)
Both corrections are correct.
I quickly cheched the other 2 cps instrcutions (Thumb 16 & 32 bit);
they look correct.
Nice catch :)
Laurent
prev parent reply other threads:[~2008-06-12 19:58 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-06-12 19:17 [Qemu-devel] [PATCH] ARM: fix CPS instruction Vincent Palatin
2008-06-12 19:58 ` Laurent Desnogues [this message]
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