From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K6swk-0001k6-2X for qemu-devel@nongnu.org; Thu, 12 Jun 2008 15:58:58 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K6swi-0001j0-AY for qemu-devel@nongnu.org; Thu, 12 Jun 2008 15:58:57 -0400 Received: from [199.232.76.173] (port=53074 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K6swi-0001iu-5A for qemu-devel@nongnu.org; Thu, 12 Jun 2008 15:58:56 -0400 Received: from wf-out-1314.google.com ([209.85.200.173]:61532) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1K6swi-0008ST-3i for qemu-devel@nongnu.org; Thu, 12 Jun 2008 15:58:56 -0400 Received: by wf-out-1314.google.com with SMTP id 27so3757976wfd.4 for ; Thu, 12 Jun 2008 12:58:53 -0700 (PDT) Message-ID: <761ea48b0806121258k28e712a9o7148e6f137db4c2e@mail.gmail.com> Date: Thu, 12 Jun 2008 21:58:53 +0200 From: "Laurent Desnogues" Subject: Re: [Qemu-devel] [PATCH] ARM: fix CPS instruction In-Reply-To: <200806122117.54077.vincent.palatin_qemu@polytechnique.org> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <200806122117.54077.vincent.palatin_qemu@polytechnique.org> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Thu, Jun 12, 2008 at 9:17 PM, Vincent Palatin wrote: > I attach a patch with 2 fixes for the ARMv6 instruction "CPS". > According to ARM Reference Manual (DDI0100 A4.1.16), > bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask > should be 0x0ff10020 not 0x0ff10010. > Besides, mmod flag is bit 17 (b14 is SBZ) Both corrections are correct. I quickly cheched the other 2 cps instrcutions (Thumb 16 & 32 bit); they look correct. Nice catch :) Laurent