[Qemu-devel] [PATCH] ARM: fix CPS instruction

[Qemu-devel] [PATCH] ARM: fix CPS instruction

[Vincent Palatin]

[-- Attachment #1: Type: text/plain, Size: 305 bytes --]

Dear developers,

I attach a patch with 2 fixes for the ARMv6 instruction "CPS".
According to ARM Reference Manual (DDI0100 A4.1.16), 
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask 
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)

-- 
Vincent

[-- Attachment #2: arm_cps.patch --]
[-- Type: text/x-diff, Size: 858 bytes --]

Index: target-arm/translate.c
===================================================================
--- target-arm/translate.c	(revision 4740)
+++ target-arm/translate.c	(working copy)
@@ -5801,7 +5801,7 @@
             /* Coprocessor double register transfer.  */
         } else if ((insn & 0x0f000010) == 0x0e000010) {
             /* Additional coprocessor register transfer.  */
-        } else if ((insn & 0x0ff10010) == 0x01000000) {
+        } else if ((insn & 0x0ff10020) == 0x01000000) {
             uint32_t mask;
             uint32_t val;
             /* cps (privileged) */
@@ -5818,7 +5818,7 @@
                 if (insn & (1 << 18))
                     val |= mask;
             }
-            if (insn & (1 << 14)) {
+            if (insn & (1 << 17)) {
                 mask |= CPSR_M;
                 val |= (insn & 0x1f);
             }

Re: [Qemu-devel] [PATCH] ARM: fix CPS instruction

[Laurent Desnogues]

On Thu, Jun 12, 2008 at 9:17 PM, Vincent Palatin
<vincent.palatin_qemu@polytechnique.org> wrote:
> I attach a patch with 2 fixes for the ARMv6 instruction "CPS".
> According to ARM Reference Manual (DDI0100 A4.1.16),
> bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
> should be  0x0ff10020 not 0x0ff10010.
> Besides, mmod flag is bit 17 (b14 is SBZ)

Both corrections are correct.

I quickly cheched the other 2 cps instrcutions (Thumb 16 & 32 bit);
they look correct.

Nice catch :)


Laurent