From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KynNX-0006fb-7Z for qemu-devel@nongnu.org; Sat, 08 Nov 2008 07:57:27 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KynNV-0006eK-Vp for qemu-devel@nongnu.org; Sat, 08 Nov 2008 07:57:26 -0500 Received: from [199.232.76.173] (port=53147 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KynNV-0006e5-Qd for qemu-devel@nongnu.org; Sat, 08 Nov 2008 07:57:25 -0500 Received: from wf-out-1314.google.com ([209.85.200.171]:32985) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KynNV-00024d-E7 for qemu-devel@nongnu.org; Sat, 08 Nov 2008 07:57:25 -0500 Received: by wf-out-1314.google.com with SMTP id 27so1757730wfd.4 for ; Sat, 08 Nov 2008 04:57:21 -0800 (PST) Message-ID: <761ea48b0811080457u6c57f1a7tf43c99903bc32d78@mail.gmail.com> Date: Sat, 8 Nov 2008 13:57:21 +0100 From: "Laurent Desnogues" Subject: Re: [Qemu-devel] [PATCH 04/11] target-mips: convert bitfield ops to TCG In-Reply-To: <20081108083416.GF9549@volta.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20081108083118.GB9549@volta.aurel32.net> <20081108083416.GF9549@volta.aurel32.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Sat, Nov 8, 2008 at 9:34 AM, Aurelien Jarno wrote: > Bitfield operations can be written with very few TCG instructions > (between 2 and 5), so it is worth converting them to TCG. > > Signed-off-by: Aurelien Jarno > --- > target-mips/helper.h | 6 +---- > target-mips/op_helper.c | 26 +------------------------ > target-mips/translate.c | 49 +++++++++++++++++++++++++++++++++++++--------- > 3 files changed, 41 insertions(+), 40 deletions(-) [...] > diff --git a/target-mips/translate.c b/target-mips/translate.c > index af01f73..2cd1868 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -2682,57 +2682,86 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, > static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, > int rs, int lsb, int msb) > { > - TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); > - TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL); > + TCGv t0 = tcg_temp_new(TCG_TYPE_TL); > + TCGv t1 = tcg_temp_new(TCG_TYPE_TL); > + target_ulong mask; > > gen_load_gpr(t1, rs); > switch (opc) { > case OPC_EXT: > if (lsb + msb > 31) > goto fail; > - tcg_gen_helper_1_1ii(do_ext, t0, t1, lsb, msb + 1); > + tcg_gen_shri_tl(t0, t1, lsb); > + if (msb + 1 < 32) { Given the above restriction of lsb + msb <= 31, this test can be rewritten as: if (msb != 31) I find this more readable, but that's personal taste :-) > + tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1); > + } else { > + tcg_gen_ext32s_tl(t0, t0); > + } > break; > #if defined(TARGET_MIPS64) > case OPC_DEXTM: > if (lsb + msb > 63) > goto fail; Can this really happen? lsb and msb are 5 bit wide as far as I could see. > - tcg_gen_helper_1_1ii(do_dext, t0, t1, lsb, msb + 1 + 32); > + tcg_gen_shri_tl(t0, t1, lsb); > + if (msb + 1 + 32 < 64) { This can be rewritten as if (msb != 31) > + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1); > + } > break; > case OPC_DEXTU: > if (lsb + msb > 63) > goto fail; Same as above. > - tcg_gen_helper_1_1ii(do_dext, t0, t1, lsb + 32, msb + 1); > + tcg_gen_shri_tl(t0, t1, lsb + 32); > + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1); > break; > case OPC_DEXT: > if (lsb + msb > 63) > goto fail; Same as above. Laurent