From: "Laurent Desnogues" <laurent.desnogues@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATH] ARM: some fixes
Date: Tue, 25 Nov 2008 19:40:30 +0100 [thread overview]
Message-ID: <761ea48b0811251040q78e57e4eobca3151ded23f761@mail.gmail.com> (raw)
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Hello,
this patch fixes some bugs and inaccuracies in ARM translator:
- gen_set_CF_bit31: use the right value to set carry flag
- shifter_out_im: remove a spurious semi-colon
- add a break for VSHRN, VRSHRN, VQSHRN, VQRSHRN
size 2 case
- sbfx, ubfx are v6t2 instructions
- cps is undefined in user mode (only fixed for ARM
instruction set)
Laurent
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
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Index: target-arm/translate.c
===================================================================
--- target-arm/translate.c (revision 5796)
+++ target-arm/translate.c (working copy)
@@ -421,7 +421,7 @@
{
TCGv tmp = new_tmp();
tcg_gen_shri_i32(tmp, var, 31);
- gen_set_CF(var);
+ gen_set_CF(tmp);
dead_tmp(tmp);
}
@@ -496,7 +496,7 @@
tcg_gen_andi_i32(tmp, var, 1);
} else {
tcg_gen_shri_i32(tmp, var, shift);
- if (shift != 31);
+ if (shift != 31)
tcg_gen_andi_i32(tmp, tmp, 1);
}
gen_set_CF(tmp);
@@ -4644,6 +4644,7 @@
imm = (uint32_t)shift;
tmp2 = tcg_const_i32(imm);
TCGV_UNUSED_I64(tmp64);
+ break;
case 3:
tmp64 = tcg_const_i64(shift);
TCGV_UNUSED(tmp2);
@@ -6609,6 +6610,7 @@
break;
case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
+ ARCH(6T2);
tmp = load_reg(s, rm);
shift = (insn >> 7) & 0x1f;
i = ((insn >> 16) & 0x1f) + 1;
@@ -8475,7 +8477,7 @@
case 6: /* cps */
ARCH(6);
if (IS_USER(s))
- break;
+ goto illegal_op;
if (IS_M(env)) {
tmp = tcg_const_i32((insn & (1 << 4)) != 0);
/* PRIMASK */
reply other threads:[~2008-11-25 18:40 UTC|newest]
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