From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1L5Fy2-0005Kk-6C for qemu-devel@nongnu.org; Wed, 26 Nov 2008 03:41:50 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1L5Fy0-0005KY-Mc for qemu-devel@nongnu.org; Wed, 26 Nov 2008 03:41:48 -0500 Received: from [199.232.76.173] (port=52623 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1L5Fy0-0005KV-J8 for qemu-devel@nongnu.org; Wed, 26 Nov 2008 03:41:48 -0500 Received: from fg-out-1718.google.com ([72.14.220.156]:5717) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1L5Fy0-0005Af-2q for qemu-devel@nongnu.org; Wed, 26 Nov 2008 03:41:48 -0500 Received: by fg-out-1718.google.com with SMTP id l26so239821fgb.8 for ; Wed, 26 Nov 2008 00:41:47 -0800 (PST) Message-ID: <761ea48b0811260041x3a5712f4n8a246b7f17ddd6c7@mail.gmail.com> Date: Wed, 26 Nov 2008 09:41:47 +0100 From: "Laurent Desnogues" Subject: Re: [Qemu-devel] [PATCH] ARM: fix smmul and smmla instructions In-Reply-To: <1227655631-7852-1-git-send-email-mans@mansr.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <1227655631-7852-1-git-send-email-mans@mansr.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Wed, Nov 26, 2008 at 12:27 AM, Mans Rullgard wrote: > This fixes the destination and accumulator registers for the smmul > and smmla instructions. This patch is correct. Laurent > Signed-off-by: Mans Rullgard > --- > target-arm/translate.c | 6 +++--- > 1 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 305a438..49e48c5 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -6507,8 +6507,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) > tcg_gen_shri_i64(tmp64, tmp64, 32); > tmp = new_tmp(); > tcg_gen_trunc_i64_i32(tmp, tmp64); > - if (rn != 15) { > - tmp2 = load_reg(s, rn); > + if (rd != 15) { > + tmp2 = load_reg(s, rd); > if (insn & (1 << 6)) { > tcg_gen_sub_i32(tmp, tmp, tmp2); > } else { > @@ -6516,7 +6516,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) > } > dead_tmp(tmp2); > } > - store_reg(s, rd, tmp); > + store_reg(s, rn, tmp); > } else { > if (insn & (1 << 5)) > gen_swap_half(tmp2); > -- > 1.6.0.4 > > > >