[Qemu-devel] [PATCH] ARM: some more cleanups and potential bug fixes

[Qemu-devel] [PATCH] ARM: some more cleanups and potential bug fixes

[Laurent Desnogues]

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Hello,

this patch fixes a few things in some ARM target files.

1. op_helper.c:  add_cc should used its parameters;  this
   worked because the helper is currently called with
   cpu_T[01], but if someone decides to remove cpu_T
   this will be wrong

2. translate.c
   - typos
   - extraneous semi colons
   - extraneous break
   - unused functions removal.

HTH,

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>

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Index: target-arm/op_helper.c
===================================================================
--- target-arm/op_helper.c	(revision 5918)
+++ target-arm/op_helper.c	(working copy)
@@ -307,7 +307,7 @@
 uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
 {
     uint32_t result;
-    result = T0 + T1;
+    result = a + b;
     env->NF = env->ZF = result;
     env->CF = result < a;
     env->VF = (a ^ b ^ -1) & (a ^ result);
Index: target-arm/translate.c
===================================================================
--- target-arm/translate.c	(revision 5918)
+++ target-arm/translate.c	(working copy)
@@ -160,7 +160,7 @@
 {
     if (reg == 15) {
         uint32_t addr;
-        /* normaly, since we updated PC, we need only to add one insn */
+        /* normally, since we updated PC, we need only to add one insn */
         if (s->thumb)
             addr = (long)s->pc + 2;
         else
@@ -214,8 +214,8 @@
 #define gen_op_orl_T0_T1() tcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_T[1])
 #define gen_op_notl_T0() tcg_gen_not_i32(cpu_T[0], cpu_T[0])
 #define gen_op_notl_T1() tcg_gen_not_i32(cpu_T[1], cpu_T[1])
-#define gen_op_logic_T0_cc() gen_logic_CC(cpu_T[0]);
-#define gen_op_logic_T1_cc() gen_logic_CC(cpu_T[1]);
+#define gen_op_logic_T0_cc() gen_logic_CC(cpu_T[0])
+#define gen_op_logic_T1_cc() gen_logic_CC(cpu_T[1])
 
 #define gen_op_shll_T1_im(im) tcg_gen_shli_i32(cpu_T[1], cpu_T[1], im)
 #define gen_op_shrl_T1_im(im) tcg_gen_shri_i32(cpu_T[1], cpu_T[1], im)
@@ -534,7 +534,7 @@
         if (shift != 0) {
             if (flags)
                 shifter_out_im(var, shift - 1);
-            tcg_gen_rori_i32(var, var, shift); break;
+            tcg_gen_rori_i32(var, var, shift);
         } else {
             TCGv tmp = load_cpu_field(CF);
             if (flags)
@@ -545,7 +545,7 @@
             dead_tmp(tmp);
         }
     }
-};
+}
 
 static inline void gen_arm_shift_reg(TCGv var, int shiftop,
                                      TCGv shift, int flags)
@@ -803,14 +803,6 @@
     store_cpu_field(var, regs[15]);
 }
 
-/* TODO: This should be removed.  Use gen_bx instead.  */
-static inline void gen_bx_T0(DisasContext *s)
-{
-    TCGv tmp = new_tmp();
-    tcg_gen_mov_i32(tmp, cpu_T[0]);
-    gen_bx(s, tmp);
-}
-
 static inline TCGv gen_ld8s(TCGv addr, int index)
 {
     TCGv tmp = new_tmp();
@@ -867,11 +859,6 @@
     load_reg_var(s, cpu_T[1], reg);
 }
 
-static inline void gen_movl_T2_reg(DisasContext *s, int reg)
-{
-    load_reg_var(s, cpu_T[2], reg);
-}
-
 static inline void gen_set_pc_im(uint32_t val)
 {
     TCGv tmp = new_tmp();
@@ -3600,15 +3587,6 @@
   tcg_gen_ld_i32(cpu_T[0], cpu_env, offset);
 }
 
-static inline void
-gen_neon_movl_T1_scratch(int scratch)
-{
-  uint32_t offset;
-
-  offset = offsetof(CPUARMState, vfp.scratch[scratch]);
-  tcg_gen_ld_i32(cpu_T[1], cpu_env, offset);
-}
-
 static inline void gen_neon_get_scalar(int size, int reg)
 {
     if (size == 1) {
@@ -4446,7 +4424,7 @@
                     size--;
             }
             shift = (insn >> 16) & ((1 << (3 + size)) - 1);
-            /* To avoid excessive dumplication of ops we implement shift
+            /* To avoid excessive duplication of ops we implement shift
                by immediate using the variable shift operations.  */
             if (op < 8) {
                 /* Shift by immediate:
@@ -5042,7 +5020,7 @@
                         NEON_SET_REG(T0, rd, pass);
                     }
                     break;
-                case 2: /* VMLAL sclar */
+                case 2: /* VMLAL scalar */
                 case 3: /* VQDMLAL scalar */
                 case 6: /* VMLSL scalar */
                 case 7: /* VQDMLSL scalar */
@@ -8751,7 +8729,7 @@
     } else {
         /* While branches must always occur at the end of an IT block,
            there are a few other things that can cause us to terminate
-           the TB in the middel of an IT block:
+           the TB in the middle of an IT block:
             - Exception generating instructions (bkpt, swi, undefined).
             - Page boundaries.
             - Hardware watchpoints.