[Qemu-devel] [PATCH] ARM back-end: Handle all possible immediates for ALU ops

[Qemu-devel] [PATCH] ARM back-end: Handle all possible immediates for ALU ops

[Laurent Desnogues]

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Hello,

this patch handles all possible constants for immediate operand of ALU ops.
I'm not very satisfied by the implementation.


Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>

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diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 7ef2b89..5625f6e 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -180,10 +180,37 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 }
 
 
+static inline uint32_t rotl(uint32_t val, int n)
+{
+  return (val << n) | (val >> (32 - n));
+}
+
+
+/* ARM immediates for ALU instructions are made of an unsigned 8-bit
+   right-rotated by an even amount between 0 and 30. */
+static inline int encode_imm(uint32_t imm)
+{
+    int shift;
+
+    /* simple case, only lower bits */
+    if ((imm & ~0xff) == 0)
+        return 0;
+    /* then try a simple even shift */
+    shift = ctz32(imm) & ~1;
+    if (((imm >> shift) & ~0xff) == 0)
+        return 32 - shift;
+    /* now try harder with rotations */
+    for (shift = 2; shift < 32; shift += 2) {
+        if ((rotl(imm, shift) & ~0xff) == 0)
+            return shift;
+    }
+    /* imm can't be encoded */
+    return -1;
+}
+
 static inline int check_fit_imm(uint32_t imm)
 {
-    /* XXX: use rotation */
-    return (imm & ~0xff) == 0;
+    return encode_imm(imm) >= 0;
 }
 
 /* Test if a constant matches the constraint.
@@ -1407,10 +1434,12 @@ static inline void tcg_out_op(TCGContext *s, int opc,
         c = ARITH_EOR;
         /* Fall through.  */
     gen_arith:
-        if (const_args[2])
+        if (const_args[2]) {
+            int rot;
+            rot = encode_imm(args[2]);
             tcg_out_dat_imm(s, COND_AL, c,
-                            args[0], args[1], args[2]);
-        else
+                            args[0], args[1], rotl(args[2], rot) | (rot << 7));
+        } else
             tcg_out_dat_reg(s, COND_AL, c,
                             args[0], args[1], args[2], SHIFT_IMM_LSL(0));
         break;
@@ -1427,6 +1456,10 @@ static inline void tcg_out_op(TCGContext *s, int opc,
     case INDEX_op_neg_i32:
         tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
         break;
+    case INDEX_op_not_i32:
+        tcg_out_dat_reg(s, COND_AL,
+                        ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
+        break;
     case INDEX_op_mul_i32:
         tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
         break;
@@ -1555,12 +1588,13 @@ static const TCGTargetOpDef arm_op_defs[] = {
     { INDEX_op_sub_i32, { "r", "r", "rI" } },
     { INDEX_op_mul_i32, { "r", "r", "r" } },
     { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
-    { INDEX_op_div2_i32, { "r", "r", "r", "1", "2" } },
-    { INDEX_op_divu2_i32, { "r", "r", "r", "1", "2" } },
+    { INDEX_op_div2_i32, { "r", "r", "r", "0", "1" } },
+    { INDEX_op_divu2_i32, { "r", "r", "r", "0", "1" } },
     { INDEX_op_and_i32, { "r", "r", "rI" } },
     { INDEX_op_or_i32, { "r", "r", "rI" } },
     { INDEX_op_xor_i32, { "r", "r", "rI" } },
     { INDEX_op_neg_i32, { "r", "r" } },
+    { INDEX_op_not_i32, { "r", "r" } },
 
     { INDEX_op_shl_i32, { "r", "r", "ri" } },
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 7ff2928..71e1ec5 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -33,6 +33,7 @@
 #define TCG_TARGET_HAS_ext16s_i32
 #define TCG_TARGET_HAS_neg_i32
 #undef TCG_TARGET_HAS_neg_i64
+#define TCG_TARGET_HAS_not_i32
 #undef TCG_TARGET_STACK_GROWSUP
 
 enum {

Re: [Qemu-devel] [PATCH] ARM back-end: Handle all possible immediates for ALU ops

[andrzej zaborowski]

2009/7/24 Laurent Desnogues <laurent.desnogues@gmail.com>:
> Hello,
>
> this patch handles all possible constants for immediate operand of ALU ops.
> I'm not very satisfied by the implementation.

I "unrolled" the loop because only three of the values were
satisfiable (I think), but haven't tested.

Cheers