From: Laurent Desnogues <laurent.desnogues@gmail.com>
To: andrzej zaborowski <balrogg@gmail.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] ARM back-end: Fix register numbering for div/divu and add TCG not
Date: Fri, 25 Sep 2009 17:46:29 +0200 [thread overview]
Message-ID: <761ea48b0909250846y6ebe4fcepff1219a637cbcea6@mail.gmail.com> (raw)
In-Reply-To: <fb249edb0908220503q4fd9e1e6u69f9e78a2535716d@mail.gmail.com>
On Sat, Aug 22, 2009 at 2:03 PM, andrzej zaborowski <balrogg@gmail.com> wrote:
> 2009/7/24 Laurent Desnogues <laurent.desnogues@gmail.com>:
>> Hello,
>>
>> this patch:
>>
>> - fixes argument numbers for div2 and divu2
>
> But "0" is not defined in target_parse_constraint? Does div2 not work
> as is now?
Given Gary Thomas latest question, I guess it's time to
resurrect that discussion :-)
Constraints defined as numbers are handled internally
by TCG in tcg_add_target_add_op_defs. My understanding
is that they mean that an input and an output arg are aliased.
I don't think it's what the constraint for div2 and divu2 is
trying to express.
Also the div helper looks broken: it potentially restores less
registers than what it saved, and uses ldrt.
My proposed fix was completely wrong, but I have no time
to make a correct one.
Laurent
prev parent reply other threads:[~2009-09-25 15:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-07-24 17:23 [Qemu-devel] [PATCH] ARM back-end: Fix register numbering for div/divu and add TCG not Laurent Desnogues
2009-07-24 18:01 ` Filip Navara
2009-07-24 18:54 ` Laurent Desnogues
2009-08-22 12:03 ` andrzej zaborowski
2009-09-25 15:46 ` Laurent Desnogues [this message]
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