* [Qemu-devel] [PATCH 06/12] target-arm: optimize arm load/store multiple ops
@ 2009-10-21 10:17 Juha.Riihimaki
2009-10-23 22:48 ` Laurent Desnogues
0 siblings, 1 reply; 2+ messages in thread
From: Juha.Riihimaki @ 2009-10-21 10:17 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2605 bytes --]
ARM load/store multiple instructions can be slightly optimized by
loading the register offset constant into a variable outside the
register loop and using the preloaded variable inside the loop instead
of reloading the offset value to a temporary variable on each loop
iteration. This causes less TCG ops to be generated for a ARM load/
store multiple instruction.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
---
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e5a2881..bae1122 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6852,6 +6852,7 @@ static void disas_arm_insn(CPUState * env,
DisasContext *s)
}
rn = (insn >> 16) & 0xf;
addr = load_reg(s, rn);
+ tmp2 = tcg_const_i32(4);
/* compute total size */
loaded_base = 0;
@@ -6865,7 +6866,7 @@ static void disas_arm_insn(CPUState * env,
DisasContext *s)
if (insn & (1 << 23)) {
if (insn & (1 << 24)) {
/* pre increment */
- tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_add_i32(addr, addr, tmp2);
} else {
/* post increment */
}
@@ -6918,7 +6919,7 @@ static void disas_arm_insn(CPUState * env,
DisasContext *s)
j++;
/* no need to add after the last transfer */
if (j != n)
- tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_add_i32(addr, addr, tmp2);
}
}
if (insn & (1 << 21)) {
@@ -6928,7 +6929,7 @@ static void disas_arm_insn(CPUState * env,
DisasContext *s)
/* pre increment */
} else {
/* post increment */
- tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_add_i32(addr, addr, tmp2);
}
} else {
if (insn & (1 << 24)) {
@@ -6944,6 +6945,7 @@ static void disas_arm_insn(CPUState * env,
DisasContext *s)
} else {
dead_tmp(addr);
}
+ tcg_temp_free_i32(tmp2);
if (loaded_base) {
store_reg(s, rn, loaded_var);
}
[-- Attachment #2: translate.c.ldmstm.diff --]
[-- Type: application/octet-stream, Size: 2117 bytes --]
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e5a2881..bae1122 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6852,6 +6852,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
}
rn = (insn >> 16) & 0xf;
addr = load_reg(s, rn);
+ tmp2 = tcg_const_i32(4);
/* compute total size */
loaded_base = 0;
@@ -6865,7 +6866,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
if (insn & (1 << 23)) {
if (insn & (1 << 24)) {
/* pre increment */
- tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_add_i32(addr, addr, tmp2);
} else {
/* post increment */
}
@@ -6918,7 +6919,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
j++;
/* no need to add after the last transfer */
if (j != n)
- tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_add_i32(addr, addr, tmp2);
}
}
if (insn & (1 << 21)) {
@@ -6928,7 +6929,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
/* pre increment */
} else {
/* post increment */
- tcg_gen_addi_i32(addr, addr, 4);
+ tcg_gen_add_i32(addr, addr, tmp2);
}
} else {
if (insn & (1 << 24)) {
@@ -6944,6 +6945,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
} else {
dead_tmp(addr);
}
+ tcg_temp_free_i32(tmp2);
if (loaded_base) {
store_reg(s, rn, loaded_var);
}
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH 06/12] target-arm: optimize arm load/store multiple ops
2009-10-21 10:17 [Qemu-devel] [PATCH 06/12] target-arm: optimize arm load/store multiple ops Juha.Riihimaki
@ 2009-10-23 22:48 ` Laurent Desnogues
0 siblings, 0 replies; 2+ messages in thread
From: Laurent Desnogues @ 2009-10-23 22:48 UTC (permalink / raw)
To: Juha.Riihimaki; +Cc: qemu-devel
On Wed, Oct 21, 2009 at 12:17 PM, <Juha.Riihimaki@nokia.com> wrote:
> ARM load/store multiple instructions can be slightly optimized by
> loading the register offset constant into a variable outside the
> register loop and using the preloaded variable inside the loop instead
> of reloading the offset value to a temporary variable on each loop
> iteration. This causes less TCG ops to be generated for a ARM load/
> store multiple instruction.
>
> Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> ---
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index e5a2881..bae1122 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -6852,6 +6852,7 @@ static void disas_arm_insn(CPUState * env,
> DisasContext *s)
> }
> rn = (insn >> 16) & 0xf;
> addr = load_reg(s, rn);
> + tmp2 = tcg_const_i32(4);
>
> /* compute total size */
> loaded_base = 0;
> @@ -6865,7 +6866,7 @@ static void disas_arm_insn(CPUState * env,
> DisasContext *s)
> if (insn & (1 << 23)) {
> if (insn & (1 << 24)) {
> /* pre increment */
> - tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_add_i32(addr, addr, tmp2);
> } else {
> /* post increment */
> }
> @@ -6918,7 +6919,7 @@ static void disas_arm_insn(CPUState * env,
> DisasContext *s)
> j++;
> /* no need to add after the last transfer */
> if (j != n)
> - tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_add_i32(addr, addr, tmp2);
> }
> }
> if (insn & (1 << 21)) {
> @@ -6928,7 +6929,7 @@ static void disas_arm_insn(CPUState * env,
> DisasContext *s)
> /* pre increment */
> } else {
> /* post increment */
> - tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_add_i32(addr, addr, tmp2);
> }
> } else {
> if (insn & (1 << 24)) {
> @@ -6944,6 +6945,7 @@ static void disas_arm_insn(CPUState * env,
> DisasContext *s)
> } else {
> dead_tmp(addr);
> }
> + tcg_temp_free_i32(tmp2);
> if (loaded_base) {
> store_reg(s, rn, loaded_var);
> }
>
Laurent
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