From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N20oP-0001mN-Sg for qemu-devel@nongnu.org; Sun, 25 Oct 2009 06:59:01 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N20oO-0001lj-EC for qemu-devel@nongnu.org; Sun, 25 Oct 2009 06:59:00 -0400 Received: from [199.232.76.173] (port=35343 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N20oN-0001lc-LB for qemu-devel@nongnu.org; Sun, 25 Oct 2009 06:59:00 -0400 Received: from fg-out-1718.google.com ([72.14.220.154]:1535) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1N20oN-0006Gq-5q for qemu-devel@nongnu.org; Sun, 25 Oct 2009 06:58:59 -0400 Received: by fg-out-1718.google.com with SMTP id d23so3892257fga.10 for ; Sun, 25 Oct 2009 03:58:57 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1256386749-85299-2-git-send-email-juha.riihimaki@nokia.com> References: <1256386749-85299-1-git-send-email-juha.riihimaki@nokia.com> <1256386749-85299-2-git-send-email-juha.riihimaki@nokia.com> Date: Sun, 25 Oct 2009 11:58:57 +0100 Message-ID: <761ea48b0910250358l39605c13v90657bd291a1c479@mail.gmail.com> Subject: Re: [Qemu-devel] [PATCH v2 01/10] target-arm: fix neon vshrn/vrshrn ops From: Laurent Desnogues Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: juha.riihimaki@nokia.com Cc: qemu-devel@nongnu.org On Sat, Oct 24, 2009 at 1:19 PM, wrote: > From: Juha Riihim=E4ki > > In the existing code shift value is clobbered during the pass loop. > This patch changes the code so that it stores the intermediate > result in the target neon register directly and eliminates the need > to use a temporary to hold the intermediate value thus leaving the > shift value in the temporary variable intact. This is a new patch > in this version of the patch series. > > Signed-off-by: Juha Riihim=E4ki Acked-by: Laurent Desnogues Laurent > --- > =A0target-arm/translate.c | =A0 12 +++--------- > =A01 files changed, 3 insertions(+), 9 deletions(-) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 9d13d42..8a85db6 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -4680,18 +4680,12 @@ static int disas_neon_data_insn(CPUState * env, D= isasContext *s, uint32_t insn) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 gen_neon_narrow_s= atu(size - 1, tmp, cpu_V0); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 } > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (pass =3D=3D 0) { > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (size !=3D 3) { > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dead_tmp(tmp2); > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0} > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tmp2 =3D tmp; > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0} else { > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0neon_store_reg(rd, 0, tm= p2); > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0neon_store_reg(rd, 1, tm= p); > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0} > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0neon_store_reg(rd, pass, tmp); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 } /* for pass */ > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (size =3D=3D 3) { > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 tcg_temp_free_i64(tmp64); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0} else { > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dead_tmp(tmp2); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 } > =A0 =A0 =A0 =A0 =A0 =A0 } else if (op =3D=3D 10) { > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* VSHLL */ > -- > 1.6.5 > > > >