From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N228Q-0007dY-Q2 for qemu-devel@nongnu.org; Sun, 25 Oct 2009 08:23:46 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N228Q-0007d3-3K for qemu-devel@nongnu.org; Sun, 25 Oct 2009 08:23:46 -0400 Received: from [199.232.76.173] (port=49145 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N228P-0007ct-Ux for qemu-devel@nongnu.org; Sun, 25 Oct 2009 08:23:46 -0400 Received: from fg-out-1718.google.com ([72.14.220.153]:45235) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1N228P-0002Qn-Fy for qemu-devel@nongnu.org; Sun, 25 Oct 2009 08:23:45 -0400 Received: by fg-out-1718.google.com with SMTP id 16so616847fgg.10 for ; Sun, 25 Oct 2009 05:23:44 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1256386749-85299-4-git-send-email-juha.riihimaki@nokia.com> References: <1256386749-85299-1-git-send-email-juha.riihimaki@nokia.com> <1256386749-85299-4-git-send-email-juha.riihimaki@nokia.com> Date: Sun, 25 Oct 2009 13:23:44 +0100 Message-ID: <761ea48b0910250523t513f6c54t6bade67aef71cd0a@mail.gmail.com> Subject: Re: [Qemu-devel] [PATCH v2 03/10] target-arm: allow modifying vfp fpexc en bit only From: Laurent Desnogues Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: juha.riihimaki@nokia.com Cc: qemu-devel@nongnu.org On Sat, Oct 24, 2009 at 1:19 PM, wrote: > From: Juha Riihim=E4ki > > All other bits except for the EN in the VFP FPEXC register are defined > as subarchitecture specific and real functionality for any of the > other bits has not been implemented in QEMU. However, current code > allows modifying all bits in the VFP FPEXC register leading to > problems when guest code is writing 1's to the subarchitecture > specific bits and checking whether the bits stay up to verify the > existence of functionality which in fact does not exist in QEMU. Shouldn't writes to FPEXC from gdb be protected in the same way? Except for that I agree with your patch. Laurent > Signed-off-by: Juha Riihim=E4ki > --- > =A0target-arm/translate.c | =A0 =A03 +++ > =A01 files changed, 3 insertions(+), 0 deletions(-) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 09c996d..8cb1c0f 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -2788,6 +2788,9 @@ static int disas_vfp_insn(CPUState * env, DisasCont= ext *s, uint32_t insn) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case ARM_VFP_FPEXC: > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (IS_USER(s)) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 return 1; > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* TODO: VFP sub= architecture support. > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 * For now, keep= the EN bit only */ > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_andi_i32= (tmp, tmp, 1 << 30); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 store_cpu_field(t= mp, vfp.xregs[rn]); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 gen_lookup_tb(s); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break; > -- > 1.6.5 > > > >