From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N2MUE-0002qt-Lq for qemu-devel@nongnu.org; Mon, 26 Oct 2009 06:07:38 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N2MUD-0002pp-Hw for qemu-devel@nongnu.org; Mon, 26 Oct 2009 06:07:37 -0400 Received: from [199.232.76.173] (port=33569 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N2MUD-0002ph-DV for qemu-devel@nongnu.org; Mon, 26 Oct 2009 06:07:37 -0400 Received: from fg-out-1718.google.com ([72.14.220.153]:43214) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1N2MUC-0000Xn-UC for qemu-devel@nongnu.org; Mon, 26 Oct 2009 06:07:37 -0400 Received: by fg-out-1718.google.com with SMTP id 16so804752fgg.10 for ; Mon, 26 Oct 2009 03:07:35 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1256550402-94129-1-git-send-email-juha.riihimaki@nokia.com> References: <1256550402-94129-1-git-send-email-juha.riihimaki@nokia.com> Date: Mon, 26 Oct 2009 11:07:35 +0100 Message-ID: <761ea48b0910260307x4700c914s8d53e68b0532554c@mail.gmail.com> Subject: Re: [Qemu-devel] [PATCH v3] target-arm: allow modifying vfp fpexc en bit only From: Laurent Desnogues Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: juha.riihimaki@nokia.com Cc: qemu-devel@nongnu.org On Mon, Oct 26, 2009 at 10:46 AM, wrote: > From: Juha Riihim=E4ki > > All other bits except for the EN in the VFP FPEXC register are defined > as subarchitecture specific and real functionality for any of the > other bits has not been implemented in QEMU. However, current code > allows modifying all bits in the VFP FPEXC register leading to > problems when guest code is writing 1's to the subarchitecture > specific bits and checking whether the bits stay up to verify the > existence of functionality which in fact does not exist in QEMU. > This patch has been revised to include the same behavior change in > the gdb register write function. > > Signed-off-by: Juha Riihim=E4ki Acked-by: Laurent Desnogues Laurent > --- > =A0target-arm/helper.c =A0 =A0| =A0 =A02 +- > =A0target-arm/translate.c | =A0 =A03 +++ > =A02 files changed, 4 insertions(+), 1 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 701629a..ee5df59 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -233,7 +233,7 @@ static int vfp_gdb_set_reg(CPUState *env, uint8_t *bu= f, int reg) > =A0 =A0 switch (reg - nregs) { > =A0 =A0 case 0: env->vfp.xregs[ARM_VFP_FPSID] =3D ldl_p(buf); return 4; > =A0 =A0 case 1: env->vfp.xregs[ARM_VFP_FPSCR] =3D ldl_p(buf); return 4; > - =A0 =A0case 2: env->vfp.xregs[ARM_VFP_FPEXC] =3D ldl_p(buf); return 4; > + =A0 =A0case 2: env->vfp.xregs[ARM_VFP_FPEXC] =3D ldl_p(buf) & (1 << 30)= ; return 4; > =A0 =A0 } > =A0 =A0 return 0; > =A0} > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 8503b92..d19ac7f 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -2804,6 +2804,9 @@ static int disas_vfp_insn(CPUState * env, DisasCont= ext *s, uint32_t insn) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case ARM_VFP_FPEXC: > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (IS_USER(s)) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 return 1; > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* TODO: VFP sub= architecture support. > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 * For now, keep= the EN bit only */ > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_andi_i32= (tmp, tmp, 1 << 30); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 store_cpu_field(t= mp, vfp.xregs[rn]); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 gen_lookup_tb(s); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break; > -- > 1.6.5 > > > >