From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NMrMp-0004UW-7l for qemu-devel@nongnu.org; Mon, 21 Dec 2009 18:08:43 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NMrMi-0004Ts-R9 for qemu-devel@nongnu.org; Mon, 21 Dec 2009 18:08:41 -0500 Received: from [199.232.76.173] (port=57049 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NMrMi-0004Tp-Lt for qemu-devel@nongnu.org; Mon, 21 Dec 2009 18:08:36 -0500 Received: from mail-pz0-f188.google.com ([209.85.222.188]:50180) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NMrMi-0008Nx-D4 for qemu-devel@nongnu.org; Mon, 21 Dec 2009 18:08:36 -0500 Received: by pzk26 with SMTP id 26so3337446pzk.4 for ; Mon, 21 Dec 2009 15:08:35 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <4B2FFBA3.4060601@twiddle.net> References: <200912202257.22503.paul@codesourcery.com> <4B2ED6D0.1010900@twiddle.net> <761ea48b0912210113p42608776q7677f79eec83f5a6@mail.gmail.com> <4B2FDA53.6040605@twiddle.net> <761ea48b0912211421y2e213dc0gfed24835f3b7f658@mail.gmail.com> <4B2FFBA3.4060601@twiddle.net> Date: Tue, 22 Dec 2009 00:08:35 +0100 Message-ID: <761ea48b0912211508i481286b8gcb78c34afb4e26ea@mail.gmail.com> Subject: Re: [Qemu-devel] [PATCH 0/5] tcg conditional set, round 4 From: Laurent Desnogues Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Paul Brook , aurelien@aurel32.net, qemu-devel@nongnu.org On Mon, Dec 21, 2009 at 11:50 PM, Richard Henderson wrote= : [...] >> Even if movcond was quick to generate >> host code, for instance for ARM, you'd have to explicitly detect >> conditional moves > > One of us is confused. =A0Why would I have to explicitly detect condition= al > moves? Most ARM instructions are conditional, with condition code being the top 4 bits of the instruction. So the front-end does it the simplest way possible: if (cond !=3D 0xe) { /* if not always execute, we generate a conditional jump to next instruction */ s->condlabel =3D gen_new_label(); gen_test_cc(cond ^ 1, s->condlabel); s->condjmp =3D 1; } and then generates the code for the instruction as if it wasn't conditional. If you wanted to use movcond, you'd have to make cond + move a special case, which would add some cost to all conditional instructions. OTOH that cost could be amortized by generating less TCG ops for that instruction, and by a potentially faster generated code. But if this isn't measured I won't bet which one is faster, I have been wrong too often. Laurent