From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NN2to-0006Fh-Qr for qemu-devel@nongnu.org; Tue, 22 Dec 2009 06:27:32 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NN2tj-0006F3-Cl for qemu-devel@nongnu.org; Tue, 22 Dec 2009 06:27:31 -0500 Received: from [199.232.76.173] (port=42045 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NN2tj-0006F0-7i for qemu-devel@nongnu.org; Tue, 22 Dec 2009 06:27:27 -0500 Received: from mail-px0-f189.google.com ([209.85.216.189]:49086) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NN2ti-0001yM-Sq for qemu-devel@nongnu.org; Tue, 22 Dec 2009 06:27:27 -0500 Received: by pxi27 with SMTP id 27so2551555pxi.4 for ; Tue, 22 Dec 2009 03:27:25 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <08eb5a18dde9c9a676073d179003398473ca311c.1261248772.git.rth@twiddle.net> References: <08eb5a18dde9c9a676073d179003398473ca311c.1261248772.git.rth@twiddle.net> Date: Tue, 22 Dec 2009 12:27:25 +0100 Message-ID: <761ea48b0912220327g8184dddu20323f5c32cd390a@mail.gmail.com> Subject: Re: [Qemu-devel] [PATCH 1/5] tcg: Generic support for conditional set From: Laurent Desnogues Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: aurelien@aurel32.net Cc: qemu-devel@nongnu.org, Richard Henderson On Sat, Dec 19, 2009 at 7:01 PM, Richard Henderson wrote: > Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit. > > Signed-off-by: Richard Henderson > --- > =A0tcg/README =A0 =A0| =A0 20 +++++++++++++++++++- > =A0tcg/tcg-op.h =A0| =A0 47 +++++++++++++++++++++++++++++++++++++++++++++= ++ > =A0tcg/tcg-opc.h | =A0 =A03 +++ > =A0tcg/tcg.c =A0 =A0 | =A0 21 +++++++++++++++------ > =A04 files changed, 84 insertions(+), 7 deletions(-) [...] > diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h > index faf2e8b..70a75a0 100644 > --- a/tcg/tcg-op.h > +++ b/tcg/tcg-op.h > @@ -280,6 +280,32 @@ static inline void tcg_gen_op6_i64(int opc, TCGv_i64= arg1, TCGv_i64 arg2, > =A0 =A0 *gen_opparam_ptr++ =3D GET_TCGV_I64(arg6); > =A0} > > +static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg= 2, > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= TCGv_i32 arg3, TCGv_i32 arg4, > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= TCGv_i32 arg5, TCGArg arg6) > +{ > + =A0 =A0*gen_opc_ptr++ =3D opc; > + =A0 =A0*gen_opparam_ptr++ =3D GET_TCGV_I32(arg1); > + =A0 =A0*gen_opparam_ptr++ =3D GET_TCGV_I32(arg2); > + =A0 =A0*gen_opparam_ptr++ =3D GET_TCGV_I32(arg3); > + =A0 =A0*gen_opparam_ptr++ =3D GET_TCGV_I32(arg4); > + =A0 =A0*gen_opparam_ptr++ =3D GET_TCGV_I32(arg5); > + =A0 =A0*gen_opparam_ptr++ =3D arg6; > +} > + > +static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg= 2, > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= TCGv_i64 arg3, TCGv_i64 arg4, > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= TCGv_i64 arg5, TCGArg arg6) > +{ > + =A0 =A0*gen_opc_ptr++ =3D opc; > + =A0 =A0*gen_opparam_ptr++ =3D GET_TCGV_I64(arg1); > + =A0 =A0*gen_opparam_ptr++ =3D GET_TCGV_I64(arg2); > + =A0 =A0*gen_opparam_ptr++ =3D GET_TCGV_I64(arg3); > + =A0 =A0*gen_opparam_ptr++ =3D GET_TCGV_I64(arg4); > + =A0 =A0*gen_opparam_ptr++ =3D GET_TCGV_I64(arg5); > + =A0 =A0*gen_opparam_ptr++ =3D arg6; > +} > + > =A0static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 = arg2, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0TCGArg arg6) > @@ -1795,6 +1821,25 @@ static inline void tcg_gen_rotri_i64(TCGv_i64 ret,= TCGv_i64 arg1, int64_t arg2) > =A0 =A0 } > =A0} > > +static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret, > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 TCGv_i32 arg1, TCGv_i32 arg2) > +{ > + =A0 =A0tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond); > +} > + > +static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret, > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 TCGv_i64 arg1, TCGv_i64 arg2) > +{ > +#if TCG_TARGET_REG_BITS =3D=3D 64 > + =A0 =A0tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond); > +#else > + =A0 =A0tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 TCGV_LOW(arg1), TCGV_HIGH(arg1)= , > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 TCGV_LOW(arg2), TCGV_HIGH(arg2)= , cond); > + =A0 =A0tcg_gen_movi_i32(TCGV_HIGH(ret), 0); > +#endif > +} I wonder if it wouldn't be better to let the back-ends emit the clearing of TCGV_HIGH(ret). This would reduce the number of emitted TCG ops. Any thoughts? Laurent