From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NN5zy-0000D2-SB for qemu-devel@nongnu.org; Tue, 22 Dec 2009 09:46:06 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NN5zu-00008l-NQ for qemu-devel@nongnu.org; Tue, 22 Dec 2009 09:46:06 -0500 Received: from [199.232.76.173] (port=39141 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NN5zu-00008c-Da for qemu-devel@nongnu.org; Tue, 22 Dec 2009 09:46:02 -0500 Received: from mail-pz0-f188.google.com ([209.85.222.188]:49066) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NN5zu-0008Fq-0j for qemu-devel@nongnu.org; Tue, 22 Dec 2009 09:46:02 -0500 Received: by pzk26 with SMTP id 26so3729336pzk.4 for ; Tue, 22 Dec 2009 06:46:01 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <4B300C8A.2030706@twiddle.net> References: <200912202257.22503.paul@codesourcery.com> <4B2ED6D0.1010900@twiddle.net> <761ea48b0912210113p42608776q7677f79eec83f5a6@mail.gmail.com> <4B2FDA53.6040605@twiddle.net> <761ea48b0912211421y2e213dc0gfed24835f3b7f658@mail.gmail.com> <4B2FFBA3.4060601@twiddle.net> <761ea48b0912211508i481286b8gcb78c34afb4e26ea@mail.gmail.com> <4B300C8A.2030706@twiddle.net> Date: Tue, 22 Dec 2009 15:46:00 +0100 Message-ID: <761ea48b0912220646h9951f0br21e9232a5d54e63c@mail.gmail.com> Subject: Re: [Qemu-devel] [PATCH 0/5] tcg conditional set, round 4 From: Laurent Desnogues Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Paul Brook , aurelien@aurel32.net, qemu-devel@nongnu.org On Tue, Dec 22, 2009 at 1:02 AM, Richard Henderson wrote: > On 12/21/2009 03:08 PM, Laurent Desnogues wrote: >> >> If you wanted to use movcond, you'd have to make >> cond + move a special case... > > You'd certainly want the ARM front-end to use movcond more often than tha= t. > =A0For instance: > > =A0addeq r1,r2,r3 > --> > =A0add_i32 tmp,r2,r3 > =A0movcond_i32 r1,ZF,0,tmp,r1,eq > > You'd want to continue to use a branch around if the instruction has side > effects like cpu fault (e.g. load, store) or updating flags. > > It ought not be very hard to arrange for something like > > =A0if (cond !=3D 0xe) { > =A0 =A0if (may_use_movcond(insn)) { > =A0 =A0 =A0s->condlabel =3D -1; > =A0 =A0 =A0/* Save the true destination register. =A0*/ > =A0 =A0 =A0s->conddest =3D cpu_R[dest]; > =A0 =A0 =A0/* Implement the instruction into a temporary. =A0*/ > =A0 =A0 =A0cpu_R[dest] =3D tcg_temp_new(); > =A0 =A0} else { > =A0 =A0 =A0s->condlabel =3D gen_new_label(); > =A0 =A0 =A0ArmConditional cmp =3D gen_test_cc(cond ^ 1); > =A0 =A0 =A0tcg_gen_brcondi_i32(cmp.cond, cmp.reg, 0, s->condlabel); > =A0 =A0} > =A0 =A0s->condjmp =3D 1; > =A0} > > =A0// ... implement the instruction as we currently do. > > =A0if (s->condjmp) { > =A0 =A0if (s->condlabel =3D=3D -1) { > =A0 =A0 =A0/* Conditionally move the temporary result into the > =A0 =A0 =A0 =A0 true destination register. =A0*/ > =A0 =A0 =A0ArmConditional cmp =3D gen_test_cc(cond); > =A0 =A0 =A0tcg_gen_movcond_i32(cmp.cond, s->conddest, cmp.reg, 0, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0cpu_R[dest], s->condde= st); > =A0 =A0 =A0tcg_temp_free(cpu_R[dest]); > =A0 =A0 =A0/* Restore the true destination register. =A0*/ > =A0 =A0 =A0cpu_R[dest] =3D s->conddest; > =A0 =A0} else { > =A0 =A0 =A0tcg_set_label(d->condlabel); > =A0 =A0} > =A0} I agree, that looks nice. But I'll let you dig into ARM instruction encoding and see how to implement may_use_movcond and getting the correct dest to save is not that cheap (and before you get back to me, yes, you could only consider a small subset of the instructions for which you want to do that :-). There's a point I have kept on insisting on that you keep on not answering :-) How does all of that perform in practice? We can discuss forever, as long as it isn't measured, we are just guessing. Laurent