From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Na8Mw-0001GD-BD for qemu-devel@nongnu.org; Wed, 27 Jan 2010 08:55:42 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Na8Mr-00019x-DR for qemu-devel@nongnu.org; Wed, 27 Jan 2010 08:55:41 -0500 Received: from [199.232.76.173] (port=46742 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Na8Mr-00019m-43 for qemu-devel@nongnu.org; Wed, 27 Jan 2010 08:55:37 -0500 Received: from mail-px0-f189.google.com ([209.85.216.189]:60508) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Na8Mq-0004iu-Ag for qemu-devel@nongnu.org; Wed, 27 Jan 2010 08:55:36 -0500 Received: by pxi27 with SMTP id 27so3881386pxi.4 for ; Wed, 27 Jan 2010 05:55:35 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1264596565-8907-5-git-send-email-riku.voipio@iki.fi> References: <1264596565-8907-1-git-send-email-riku.voipio@iki.fi> <1264596565-8907-5-git-send-email-riku.voipio@iki.fi> Date: Wed, 27 Jan 2010 14:55:35 +0100 Message-ID: <761ea48b1001270555p2d2e5adwd97ef3624f74e8df@mail.gmail.com> Subject: Re: [Qemu-devel] [PATCH 4/4] target-arm: refactor cp15.c13 register access From: Laurent Desnogues Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Riku Voipio Cc: Riku Voipio , qemu-devel@nongnu.org On Wed, Jan 27, 2010 at 1:49 PM, Riku Voipio wrote: > From: Riku Voipio > > Access the cp15.c13 TLS registers directly with TCG ops instead of with > a slow helper. If the the cp15 read/write was not TLS register access, > fall back to the cp15 helper. > > This makes accessing __thread variables in linux-user when apps are compi= led > with -mtp=3Dcp15 possible. legal cp15 register to acces from linux-user a= re > already checked in cp15_user_ok. > > While at it, make the cp15.c13 Thread ID registers available only on > ARMv6K and newer. > > Signed-off-by: Riku Voipio Acked-by: Laurent Desnogues Laurent > --- > =A0target-arm/helper.c =A0 =A0| =A0 16 -------------- > =A0target-arm/translate.c | =A0 55 ++++++++++++++++++++++++++++++++++++++= ++++++++++ > =A02 files changed, 55 insertions(+), 16 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index b3aec99..27001e8 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -511,7 +511,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, u= int32_t val) > =A0uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) > =A0{ > =A0 =A0 cpu_abort(env, "cp15 insn %08x\n", insn); > - =A0 =A0return 0; > =A0} > > =A0/* These should probably raise undefined insn exceptions. =A0*/ > @@ -1491,15 +1490,6 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn= , uint32_t val) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 tlb_flush(env, 0); > =A0 =A0 =A0 =A0 =A0 =A0 env->cp15.c13_context =3D val; > =A0 =A0 =A0 =A0 =A0 =A0 break; > - =A0 =A0 =A0 =A0case 2: > - =A0 =A0 =A0 =A0 =A0 =A0env->cp15.c13_tls1 =3D val; > - =A0 =A0 =A0 =A0 =A0 =A0break; > - =A0 =A0 =A0 =A0case 3: > - =A0 =A0 =A0 =A0 =A0 =A0env->cp15.c13_tls2 =3D val; > - =A0 =A0 =A0 =A0 =A0 =A0break; > - =A0 =A0 =A0 =A0case 4: > - =A0 =A0 =A0 =A0 =A0 =A0env->cp15.c13_tls3 =3D val; > - =A0 =A0 =A0 =A0 =A0 =A0break; > =A0 =A0 =A0 =A0 default: > =A0 =A0 =A0 =A0 =A0 =A0 goto bad_reg; > =A0 =A0 =A0 =A0 } > @@ -1779,12 +1769,6 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t = insn) > =A0 =A0 =A0 =A0 =A0 =A0 return env->cp15.c13_fcse; > =A0 =A0 =A0 =A0 case 1: > =A0 =A0 =A0 =A0 =A0 =A0 return env->cp15.c13_context; > - =A0 =A0 =A0 =A0case 2: > - =A0 =A0 =A0 =A0 =A0 =A0return env->cp15.c13_tls1; > - =A0 =A0 =A0 =A0case 3: > - =A0 =A0 =A0 =A0 =A0 =A0return env->cp15.c13_tls2; > - =A0 =A0 =A0 =A0case 4: > - =A0 =A0 =A0 =A0 =A0 =A0return env->cp15.c13_tls3; > =A0 =A0 =A0 =A0 default: > =A0 =A0 =A0 =A0 =A0 =A0 goto bad_reg; > =A0 =A0 =A0 =A0 } > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 5cf3e06..786c329 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -2455,6 +2455,57 @@ static int cp15_user_ok(uint32_t insn) > =A0 =A0 return 0; > =A0} > > +static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t = insn, uint32_t rd) > +{ > + =A0 =A0TCGv tmp; > + =A0 =A0int cpn =3D (insn >> 16) & 0xf; > + =A0 =A0int cpm =3D insn & 0xf; > + =A0 =A0int op =3D ((insn >> 5) & 7) | ((insn >> 18) & 0x38); > + > + =A0 =A0if (!arm_feature(env, ARM_FEATURE_V6K)) > + =A0 =A0 =A0 =A0return 0; > + > + =A0 =A0if (!(cpn =3D=3D 13 && cpm =3D=3D 0)) > + =A0 =A0 =A0 =A0return 0; > + > + =A0 =A0if (insn & ARM_CP_RW_BIT) { > + =A0 =A0 =A0 =A0tmp =3D new_tmp(); > + =A0 =A0 =A0 =A0switch (op) { > + =A0 =A0 =A0 =A0case 2: > + =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMStat= e, cp15.c13_tls1)); > + =A0 =A0 =A0 =A0 =A0 =A0break; > + =A0 =A0 =A0 =A0case 3: > + =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMStat= e, cp15.c13_tls2)); > + =A0 =A0 =A0 =A0 =A0 =A0break; > + =A0 =A0 =A0 =A0case 4: > + =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMStat= e, cp15.c13_tls3)); > + =A0 =A0 =A0 =A0 =A0 =A0break; > + =A0 =A0 =A0 =A0default: > + =A0 =A0 =A0 =A0 =A0 =A0dead_tmp(tmp); > + =A0 =A0 =A0 =A0 =A0 =A0return 0; > + =A0 =A0 =A0 =A0} > + =A0 =A0 =A0 =A0store_reg(s, rd, tmp); > + > + =A0 =A0} else { > + =A0 =A0 =A0 =A0tmp =3D load_reg(s, rd); > + =A0 =A0 =A0 =A0switch (op) { > + =A0 =A0 =A0 =A0case 2: > + =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMStat= e, cp15.c13_tls1)); > + =A0 =A0 =A0 =A0 =A0 =A0break; > + =A0 =A0 =A0 =A0case 3: > + =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMStat= e, cp15.c13_tls2)); > + =A0 =A0 =A0 =A0 =A0 =A0break; > + =A0 =A0 =A0 =A0case 4: > + =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMStat= e, cp15.c13_tls3)); > + =A0 =A0 =A0 =A0 =A0 =A0break; > + =A0 =A0 =A0 =A0default: > + =A0 =A0 =A0 =A0 =A0 =A0return 0; > + =A0 =A0 =A0 =A0} > + =A0 =A0 =A0 =A0dead_tmp(tmp); > + =A0 =A0} > + =A0 =A0return 1; > +} > + > =A0/* Disassemble system coprocessor (cp15) instruction. =A0Return nonzer= o if > =A0 =A0instruction is not defined. =A0*/ > =A0static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t in= sn) > @@ -2489,6 +2540,10 @@ static int disas_cp15_insn(CPUState *env, DisasCon= text *s, uint32_t insn) > =A0 =A0 =A0 =A0 return 0; > =A0 =A0 } > =A0 =A0 rd =3D (insn >> 12) & 0xf; > + > + =A0 =A0if (cp15_tls_load_store(env, s, insn, rd)) > + =A0 =A0 =A0 =A0return 0; > + > =A0 =A0 tmp2 =3D tcg_const_i32(insn); > =A0 =A0 if (insn & ARM_CP_RW_BIT) { > =A0 =A0 =A0 =A0 tmp =3D new_tmp(); > -- > 1.6.5 > > > >