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Date: Sun, 7 Feb 2010 13:54:06 +0100
Message-ID: <761ea48b1002070454j365537an16ef9a767ab8c199@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH 4/4] target-arm: neon fix
From: Laurent Desnogues <laurent.desnogues@gmail.com>
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To: Riku Voipio <riku.voipio@iki.fi>
Cc: qemu-devel@nongnu.org

On Fri, Feb 5, 2010 at 4:52 PM, Riku Voipio <riku.voipio@iki.fi> wrote:
> From: Juha Riihim=E4ki <juha.riihimaki@nokia.com>
>
> add an extra check in "two registers and a shift" to ensure element
> size decoding logic cannot fail.
>
> Signed-off-by: Juha Riihim=E4ki <juha.riihimaki@nokia.com>
> Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
> ---
> =A0target-arm/translate.c | =A0 =A03 ++-
> =A01 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 743b846..8bba034 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -4567,8 +4567,9 @@ static int disas_neon_data_insn(CPUState * env, Dis=
asContext *s, uint32_t insn)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 size =3D 3;
> =A0 =A0 =A0 =A0 =A0 =A0 } else {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 size =3D 2;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0while (size && (insn & (1 << (size + 19)=
)) =3D=3D 0)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0while (size && (insn & (1 << (size + 19)=
)) =3D=3D 0) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 size--;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0 =A0 =A0 }
> =A0 =A0 =A0 =A0 =A0 =A0 shift =3D (insn >> 16) & ((1 << (3 + size)) - 1);
> =A0 =A0 =A0 =A0 =A0 =A0 /* To avoid excessive dumplication of ops we impl=
ement shift

I think there's a patch ordering problem that makes
the comment and the change not agree :-)


Laurent