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[93.34.153.63]) by smtp.gmail.com with ESMTPSA id 35sm22266536wrj.87.2019.06.26.11.29.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 11:29:23 -0700 (PDT) To: Stefan Brankovic , qemu-devel@nongnu.org References: <1560942225-24728-1-git-send-email-stefan.brankovic@rt-rk.com> <1560942225-24728-5-git-send-email-stefan.brankovic@rt-rk.com> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <763ade00-7c85-06df-909d-eac520dd6c70@linaro.org> Date: Wed, 26 Jun 2019 17:37:16 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <1560942225-24728-5-git-send-email-stefan.brankovic@rt-rk.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: Re: [Qemu-devel] [PATCH 4/8] target/ppc: Optimize emulation of vgbbd instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/19/19 1:03 PM, Stefan Brankovic wrote: > Optimize altivec instruction vgbbd (Vector Gather Bits by Bytes by Doubleword) > All ith bits (i in range 1 to 8) of each byte of doubleword element in > source register are concatenated and placed into ith byte of appropriate > doubleword element in destination register. > > Following solution is done for both doubleword elements of source register > in parallel, in order to reduce the number of instructions needed(that's why > arrays are used): > First, both doubleword elements of source register vB are placed in > appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for > loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of > byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with > tcg_mask. For every following iteration, both avr[i] and tcg_mask variables > have to be shifted right for 7 and 8 places, respectively, in order to get > bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so > shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask... > After first 8 iteration(first loop), all the first bits are in their final > places, all second bits but second bit from eight byte are in their places... > only 1 eight bit from eight byte is in it's place). In second loop we do all > operations symmetrically, in order to get other half of bits in their final > spots. Results for first and second doubleword elements are saved in > result[0] and result[1] respectively. In the end those results are saved in > appropriate doubleword element of destination register vD. > > Signed-off-by: Stefan Brankovic > --- > target/ppc/helper.h | 1 - > target/ppc/int_helper.c | 276 ------------------------------------ > target/ppc/translate/vmx-impl.inc.c | 77 +++++++++- > 3 files changed, 76 insertions(+), 278 deletions(-) Reviewed-by: Richard Henderson r~