From: Laurent Vivier <lvivier@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-devel@nongnu.org,
Remi Denis-Courmont <remi.denis.courmont@huawei.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [Qemu-devel] [PULL 43/47] target/arm: fix AArch64 virtual address space size
Date: Fri, 8 Feb 2019 15:02:15 +0100 [thread overview]
Message-ID: <767a2e82-acf4-d282-30a2-a3f5889c01f9@redhat.com> (raw)
In-Reply-To: <20190201160653.13829-44-peter.maydell@linaro.org>
On 01/02/2019 17:06, Peter Maydell wrote:
> From: Remi Denis-Courmont <remi.denis.courmont@huawei.com>
>
> Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address,
> extension (yet), the VA address space is 48-bits plus a sign bit. User
> mode can only handle the positive half of the address space, so that
> makes a limit of 48 bits.
>
> (With LVA, it would be 53 and 52 bits respectively.)
>
> The incorrectly large address space conflicts with PAuth instructions,
> which use bits 48-54 and 56-63 for the pointer authentication code. This
> also conflicts with (as yet unsupported by QEMU) data tagging and with
> the ARMv8.5-MTE extension.
>
> Signed-off-by: Remi Denis-Courmont <remi.denis.courmont@huawei.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 63934a200ad..a68bcc9fedb 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2512,7 +2512,7 @@ bool write_cpustate_to_list(ARMCPU *cpu);
>
> #if defined(TARGET_AARCH64)
> # define TARGET_PHYS_ADDR_SPACE_BITS 48
> -# define TARGET_VIRT_ADDR_SPACE_BITS 64
> +# define TARGET_VIRT_ADDR_SPACE_BITS 48
> #else
> # define TARGET_PHYS_ADDR_SPACE_BITS 40
> # define TARGET_VIRT_ADDR_SPACE_BITS 32
>
This change breaks qemu-aarch64 (using LTP test suite):
# chroot chroot/arm64/bionic /opt/ltp/testcases/bin/access03
tst_test.c:1015: INFO: Timeout per run is 0h 05m 00s
qemu-aarch64: .../qemu/accel/tcg/translate-all.c:2522: page_check_range: Assertion `start < ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)' failed.
qemu:handle_cpu_signal received signal outside vCPU context @ pc=0x60001554
Any idea?
Thanks,
Laurent
next prev parent reply other threads:[~2019-02-08 14:02 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-01 16:06 [Qemu-devel] [PULL 00/47] target-arm queue Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 01/47] hw/arm/nrf51_soc: set object owner in memory_region_init_ram Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 02/47] armv7m: Don't assume the NVIC's CPU is CPU 0 Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 03/47] armv7m: Make cpu object a child of the armv7m container Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 04/47] armv7m: Pass through start-powered-off CPU property Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 05/47] hw/arm/iotkit: Rename IoTKit to ARMSSE Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 06/47] hw/arm/iotkit: Refactor into abstract base class and subclass Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 07/47] hw/arm/iotkit: Rename 'iotkit' local variables and functions Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 08/47] hw/arm/iotkit: Rename files to hw/arm/armsse.[ch] Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 09/47] hw/misc/iotkit-secctl: Support 4 internal MPCs Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 10/47] hw/arm/armsse: Make number of SRAM banks parameterised Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 11/47] hw/arm/armsse: Make SRAM bank size configurable Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 12/47] hw/arm/armsse: Support dual-CPU configuration Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 13/47] hw/arm/armsse: Give each CPU its own view of memory Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 14/47] hw/arm/armsse: Put each CPU in its own cluster object Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 15/47] iotkit-sysinfo: Make SYS_VERSION and SYS_CONFIG configurable Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 16/47] hw/arm/armsse: Add unimplemented-device stubs for MHUs Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 17/47] hw/arm/armsse: Add unimplemented-device stubs for PPUs Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 18/47] hw/arm/armsse: Add unimplemented-device stub for cache control registers Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 19/47] hw/arm/armsse: Add unimplemented-device stub for CPU local " Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 20/47] hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register block Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 21/47] hw/arm/armsse: Add CPU_IDENTITY block to SSE-200 Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 22/47] hw/arm/armsse: Add SSE-200 model Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 23/47] hw/arm/mps2-tz: Add IRQ infrastructure to support SSE-200 Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 24/47] hw/arm/mps2-tz: Add mps2-an521 model Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 25/47] target/arm/translate-a64: Don't underdecode system instructions Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 26/47] target/arm/translate-a64: Don't underdecode PRFM Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 27/47] target/arm/translate-a64: Don't underdecode SIMD ld/st multiple Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 28/47] target/arm/translate-a64: Don't underdecode SIMD ld/st single Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 29/47] target/arm/translate-a64: Don't underdecode add/sub extended register Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 30/47] target/arm/translate-a64: Don't underdecode FP insns Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 31/47] target/arm/translate-a64: Don't underdecode SDOT and UDOT Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 32/47] exec.c: Don't reallocate IOMMUNotifiers that are in use Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 33/47] target/arm/translate-a64: Fix FCMLA decoding error Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 34/47] target/arm/translate-a64: Fix mishandling of size in FCMLA decode Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 35/47] target/arm: Send interrupts on PMU counter overflow Peter Maydell
2020-02-25 17:08 ` Peter Maydell
2020-07-01 15:11 ` Aaron Lindsay
2020-07-03 15:14 ` Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 36/47] target/arm: Add a timer to predict " Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 37/47] target/arm: Enable API, APK bits in SCR, HCR Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 38/47] arm: Clarify the logic of set_pc() Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 39/47] target/arm: Always enable pac keys for user-only Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 40/47] aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1 Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 41/47] aarch64-linux-user: Enable HWCAP bits for PAuth Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 42/47] linux-user: Initialize aarch64 pac keys Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 43/47] target/arm: fix AArch64 virtual address space size Peter Maydell
2019-02-08 14:02 ` Laurent Vivier [this message]
2019-02-08 15:38 ` Remi Denis Courmont
2019-02-08 18:26 ` Laurent Vivier
2019-02-01 16:06 ` [Qemu-devel] [PULL 44/47] target/arm: fix decoding of B{, L}RA{A, B} Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 45/47] hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 46/47] arm: Instantiate NRF51 special NVM's and NVMC Peter Maydell
2019-02-01 16:06 ` [Qemu-devel] [PULL 47/47] tests/microbit-test: Add tests for nRF51 NVMC Peter Maydell
2019-02-01 17:56 ` [Qemu-devel] [PULL 00/47] target-arm queue Peter Maydell
2019-02-03 15:00 ` no-reply
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