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Tue, 06 Feb 2024 12:34:36 -0800 (PST) Message-ID: <768c7884-1a59-461c-a810-4f8a89d4bfda@linaro.org> Date: Wed, 7 Feb 2024 06:34:32 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/13] target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20240206132931.38376-1-peter.maydell@linaro.org> <20240206132931.38376-2-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20240206132931.38376-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/6/24 23:29, Peter Maydell wrote: > We support two different encodings for the AArch32 IMPDEF > CBAR register -- older cores like the Cortex A9, A7, A15 > have this at 4, c15, c0, 0; newer cores like the > Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0. > > When we implemented this we picked which encoding to > use based on whether the CPU set ARM_FEATURE_AARCH64. > However this isn't right for three cases: > * the qemu-system-arm 'max' CPU, which is supposed to be > a variant on a Cortex-A57; it ought to use the same > encoding the A57 does and which the AArch64 'max' > exposes to AArch32 guest code > * the Cortex-R52, which is AArch32-only but has the CBAR > at the newer encoding (and where we incorrectly are > not yet setting ARM_FEATURE_CBAR_RO anyway) > * any possible future support for other v8 AArch32 > only CPUs, or for supporting "boot the CPU into > AArch32 mode" on our existing cores like the A57 etc > > Make the decision of the encoding be based on whether > the CPU implements the ARM_FEATURE_V8 flag instead. > > This changes the behaviour only for the qemu-system-arm > '-cpu max'. We don't expect anybody to be relying on the > old behaviour because: > * it's not what the real hardware Cortex-A57 does > (and that's what our ID register claims we are) Not even that, because max resets MIDR. Anyway, Reviewed-by: Richard Henderson r~