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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-475dd042499sm139643985e9.8.2025.10.27.07.26.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Oct 2025 07:26:16 -0700 (PDT) Message-ID: <76ce5b05-98fe-4682-a5ca-2f87b7535f35@redhat.com> Date: Mon, 27 Oct 2025 15:26:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 19/27] hw/arm/smmuv3-accel: Install S1 bypass hwpt on reset Content-Language: en-US To: Nicolin Chen , Shameer Kolothum Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, peter.maydell@linaro.org, jgg@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, shameerkolothum@gmail.com References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-20-skolothumtho@nvidia.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/17/25 1:19 AM, Nicolin Chen wrote: > On Mon, Sep 29, 2025 at 02:36:35PM +0100, Shameer Kolothum wrote: >> When the guest reboots with devices in nested mode (S1 + S2), any QEMU/UEFI >> access to those devices can fail because S1 translation is not valid during >> the reboot. For example, a passthrough NVMe device may hold GRUB boot info >> that UEFI tries to read during the reboot. >> >> Set S1 to bypass mode during reset to avoid such failures. > GBPA is set to bypass on reset so I think it's fine. Yet, maybe the > code should check that. shouldn't we check its actual value before setting bypass? By the way the spec says is ABORT is set to 0x0: "Do not abort incoming transactions. Transactions bypass the SMMU with attributes given by other fields in this register." Wondering about those attributes and they can apply on the host? Eric > >> Reported-by: Matthew R. Ochs >> Signed-off-by: Shameer Kolothum >> --- >> hw/arm/smmuv3-accel.c | 29 +++++++++++++++++++++++++++++ >> hw/arm/smmuv3-accel.h | 4 ++++ >> hw/arm/smmuv3.c | 1 + >> 3 files changed, 34 insertions(+) >> >> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c >> index defeddbd8c..8396053a6c 100644 >> --- a/hw/arm/smmuv3-accel.c >> +++ b/hw/arm/smmuv3-accel.c >> @@ -634,6 +634,35 @@ static const PCIIOMMUOps smmuv3_accel_ops = { >> .get_msi_address_space = smmuv3_accel_find_msi_as, >> }; >> >> +/* >> + * If the guest reboots and devices are configured for S1+S2, Stage1 must >> + * be switched to bypass. Otherwise, QEMU/UEFI may fail when accessing a >> + * device, e.g. when UEFI retrieves boot partition information from an >> + * assigned vfio-pci NVMe device. >> + */ >> +void smmuv3_accel_attach_bypass_hwpt(SMMUv3State *s) > We could rename it to something like smmuv3_accel_reset(). > > Nicolin >