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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id b1sm1560094pfa.202.2020.04.29.11.39.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Apr 2020 11:39:42 -0700 (PDT) Subject: Re: [PATCH 1/4] target/arm: Don't use a TLB for ARMMMUIdx_Stage2 To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200330210400.11724-1-peter.maydell@linaro.org> <20200330210400.11724-2-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <771268c8-6971-e6ff-3970-ee911d1413af@linaro.org> Date: Wed, 29 Apr 2020 11:39:40 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200330210400.11724-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/30/20 2:03 PM, Peter Maydell wrote: > We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU > TLB. However we never actually use the TLB -- all stage 2 lookups > are done by direct calls to get_phys_addr_lpae() followed by a > physical address load via address_space_ld*(). > > Remove Stage2 from the list of ARM MMU indexes which correspond to > real core MMU indexes, and instead put it in the set of "NOTLB" ARM > MMU indexes. > > This allows us to drop NB_MMU_MODES to 11. It also means we can > safely add support for the ARMv8.3-TTS2UXN extension, which adds > permission bits to the stage 2 descriptors which define execute > permission separatel for EL0 and EL1; supporting that while keeping > Stage2 in a QEMU TLB would require us to use separate TLBs for > "Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a > lot of extra complication given we aren't even using the QEMU TLB. > > In the process of updating the comment on our MMU index use, > fix a couple of other minor errors: > * NS EL2 EL2&0 was missing from the list in the comment > * some text hadn't been updated from when we bumped NB_MMU_MODES > above 8 > > Signed-off-by: Peter Maydell > --- > target/arm/cpu-param.h | 2 +- > target/arm/cpu.h | 21 +++++--- > target/arm/helper.c | 112 ++++------------------------------------- > 3 files changed, 27 insertions(+), 108 deletions(-) Reviewed-by: Richard Henderson r~