From: Richard Henderson <richard.henderson@linaro.org>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: me@carlosedp.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
joel@sing.id.au, Alistair Francis <Alistair.Francis@wdc.com>,
marco@decred.org
Subject: Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
Date: Wed, 26 Jun 2019 10:30:35 +0200 [thread overview]
Message-ID: <77792d70-b438-df37-6fe4-b5723f7da99d@linaro.org> (raw)
In-Reply-To: <mhng-c3bf2d26-25cd-4f80-bfe9-741f9a969b3f@palmer-si-x1e>
On 6/26/19 10:25 AM, Palmer Dabbelt wrote:
>> You misunderstand. The code is exactly correct as-is. The alignment check
>> happens implicitly as a part of the softmmu tlb resolution.
>
> Sorry, I thought you said it wasn't happening for linux-user? If it happens
> for both then we're good.
Oh, that. No, there's no better way for linux-user. Though honestly, if we're
going to fix this, it should be done in tcg/* rather than adding hacks within
target/riscv.
r~
next prev parent reply other threads:[~2019-06-26 8:32 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-16 19:19 [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64 Joel Sing
2019-06-16 20:54 ` no-reply
2019-06-17 23:52 ` Richard Henderson
2019-06-24 6:42 ` Palmer Dabbelt
2019-06-24 18:08 ` Joel Sing
2019-06-25 15:36 ` Richard Henderson
2019-06-26 6:07 ` Palmer Dabbelt
2019-06-26 7:48 ` Richard Henderson
2019-06-26 8:25 ` Palmer Dabbelt
2019-06-26 8:30 ` Richard Henderson [this message]
2019-06-26 8:31 ` Palmer Dabbelt
2019-06-25 15:39 ` Richard Henderson
2019-06-26 6:07 ` Palmer Dabbelt
2019-09-24 18:29 ` Alistair Francis
2019-09-24 20:04 ` Palmer Dabbelt
2019-09-24 23:35 ` Alistair Francis
2019-09-25 1:01 ` Alistair Francis
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