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From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, dbarboza@ventanamicro.com,
	liwei1518@gmail.com, bmeng.cn@gmail.com,
	Huang Shiyuan <swung0x48@outlook.com>,
	TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: Re: [PATCH v5 02/12] tcg/riscv: Add basic support for vector
Date: Mon, 7 Oct 2024 09:24:34 -0700	[thread overview]
Message-ID: <77a9c9c5-9c6c-42cc-821f-1340e06ac685@linaro.org> (raw)
In-Reply-To: <20241007025700.47259-3-zhiwei_liu@linux.alibaba.com>

On 10/6/24 19:56, LIU Zhiwei wrote:
> @@ -2100,6 +2136,30 @@ static void tcg_target_init(TCGContext *s)
>   {
>       tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
>       tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
> +    s->reserved_regs = 0;
> +
> +    switch (riscv_lg2_vlenb) {
> +    case TCG_TYPE_V64:
> +        tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
> +        tcg_target_available_regs[TCG_TYPE_V128] = ALL_DVECTOR_REG_GROUPS;
> +        tcg_target_available_regs[TCG_TYPE_V256] = ALL_QVECTOR_REG_GROUPS;
> +        s->reserved_regs |= (~ALL_QVECTOR_REG_GROUPS & ALL_VECTOR_REGS);
> +        break;
> +    case TCG_TYPE_V128:
> +        tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
> +        tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
> +        tcg_target_available_regs[TCG_TYPE_V256] = ALL_DVECTOR_REG_GROUPS;
> +        s->reserved_regs |= (~ALL_DVECTOR_REG_GROUPS & ALL_VECTOR_REGS);
> +        break;
> +    default:
> +        /* Guaranteed by Zve64x. */
> +        tcg_debug_assert(riscv_lg2_vlenb >= TCG_TYPE_V256);
> +
> +        tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
> +        tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
> +        tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
> +        break;
> +    }

Missing a check for host vector support.


r~


  reply	other threads:[~2024-10-07 16:25 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-07  2:56 [PATCH v5 00/12] tcg/riscv: Add support for vector LIU Zhiwei
2024-10-07  2:56 ` [PATCH v5 01/12] util: Add RISC-V vector extension probe in cpuinfo LIU Zhiwei
2024-10-07  2:56 ` [PATCH v5 02/12] tcg/riscv: Add basic support for vector LIU Zhiwei
2024-10-07 16:24   ` Richard Henderson [this message]
2024-10-09  1:38   ` Richard Henderson
2024-10-07  2:56 ` [PATCH v5 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops LIU Zhiwei
2024-10-07 16:24   ` Richard Henderson
2024-10-08  8:51     ` LIU Zhiwei
2024-10-08 13:18       ` Richard Henderson
2024-10-07  2:56 ` [PATCH v5 04/12] tcg/riscv: Implement vector mov/dup{m/i} LIU Zhiwei
2024-10-07  2:56 ` [PATCH v5 05/12] tcg/riscv: Add support for basic vector opcodes LIU Zhiwei
2024-10-07  2:56 ` [PATCH v5 06/12] tcg/riscv: Implement vector cmp/cmpsel ops LIU Zhiwei
2024-10-07  2:56 ` [PATCH v5 07/12] tcg/riscv: Implement vector neg ops LIU Zhiwei
2024-10-07  2:56 ` [PATCH v5 08/12] tcg/riscv: Implement vector sat/mul ops LIU Zhiwei
2024-10-07  2:56 ` [PATCH v5 09/12] tcg/riscv: Implement vector min/max ops LIU Zhiwei
2024-10-07  2:56 ` [PATCH v5 10/12] tcg/riscv: Implement vector shi/s/v ops LIU Zhiwei
2024-10-07  2:56 ` [PATCH v5 11/12] tcg/riscv: Implement vector roti/v/x ops LIU Zhiwei
2024-10-07  2:57 ` [PATCH v5 12/12] tcg/riscv: Enable native vector support for TCG host LIU Zhiwei

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