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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id v65sm865642wme.31.2019.06.17.22.05.28 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 22:05:28 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20190617175317.27557-1-peter.maydell@linaro.org> <20190617175317.27557-6-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <7803c62a-c574-cefd-02b4-41df08dca085@redhat.com> Date: Tue, 18 Jun 2019 07:05:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190617175317.27557-6-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.68 Subject: Re: [Qemu-devel] [PATCH 5/6] hw/timer/armv7m_systick: Forbid non-privileged accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/17/19 7:53 PM, Peter Maydell wrote: > Like most of the v7M memory mapped system registers, the systick > registers are accessible to privileged code only and user accesses > must generate a BusFault. We implement that for registers in > the NVIC proper already, but missed it for systick since we > implement it as a separate device. Correct the omission. > > Signed-off-by: Peter Maydell > --- > hw/timer/armv7m_systick.c | 26 ++++++++++++++++++++------ > 1 file changed, 20 insertions(+), 6 deletions(-) > > diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c > index a17317ce2fe..94640743b5d 100644 > --- a/hw/timer/armv7m_systick.c > +++ b/hw/timer/armv7m_systick.c > @@ -75,11 +75,17 @@ static void systick_timer_tick(void *opaque) > } > } > > -static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size) > +static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data, > + unsigned size, MemTxAttrs attrs) > { > SysTickState *s = opaque; > uint32_t val; > > + if (attrs.user) { > + /* Generate BusFault for unprivileged accesses */ > + return MEMTX_ERROR; > + } > + > switch (addr) { > case 0x0: /* SysTick Control and Status. */ > val = s->control; > @@ -121,14 +127,21 @@ static uint64_t systick_read(void *opaque, hwaddr addr, unsigned size) > } > > trace_systick_read(addr, val, size); > - return val; > + *data = val; > + return MEMTX_OK; > } > > -static void systick_write(void *opaque, hwaddr addr, > - uint64_t value, unsigned size) > +static MemTxResult systick_write(void *opaque, hwaddr addr, > + uint64_t value, unsigned size, > + MemTxAttrs attrs) > { > SysTickState *s = opaque; > > + if (attrs.user) { > + /* Generate BusFault for unprivileged accesses */ > + return MEMTX_ERROR; > + } > + > trace_systick_write(addr, value, size); > > switch (addr) { > @@ -172,11 +185,12 @@ static void systick_write(void *opaque, hwaddr addr, > qemu_log_mask(LOG_GUEST_ERROR, > "SysTick: Bad write offset 0x%" HWADDR_PRIx "\n", addr); > } > + return MEMTX_OK; > } > > static const MemoryRegionOps systick_ops = { > - .read = systick_read, > - .write = systick_write, > + .read_with_attrs = systick_read, > + .write_with_attrs = systick_write, > .endianness = DEVICE_NATIVE_ENDIAN, > .valid.min_access_size = 4, > .valid.max_access_size = 4, > Reviewed-by: Philippe Mathieu-Daudé