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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id y19-20020a05600c20d300b003fc01f7a42dsm648858wmm.8.2023.07.10.12.28.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Jul 2023 12:28:20 -0700 (PDT) Message-ID: <781894e9-2565-b54f-8df3-9cbd1cf68e2a@linaro.org> Date: Mon, 10 Jul 2023 21:28:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 00/33] target/mips: Finalise the Ingenic MXU ASE support Content-Language: en-US To: Siarhei Volkau , qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Aurelien Jarno , Stefan Markovic , Aleksandar Markovic , Jiaxun Yang References: <20230608104222.1520143-1-lis8215@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230608104222.1520143-1-lis8215@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.101, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Siarhei, On 8/6/23 12:41, Siarhei Volkau wrote: > This patch series is aimed to add complete support of the > Ingenic MXU extensions of version 1 revision 2. > The serie doesn't split revision 1 and revision 2 of the > MXU ASE as it ought to be, because I have no hardware which > supports revision 1 only. The MXU version 2 is not the subject > of the patch series either. > > All added/fixed instructions were tested on real hardware > via set of fuzz tests written for that purpose, although > the tests aren't subject of this patch series. Thank you very much for your contribution. This is a bit unfortunate that you did'nt implemented these opcode using decodetree. Also various opcodes are not well optimized, and would benefit from using the TCG gvec API. I imagine you have been rebasing that for some years now, so I'm queuing as is to mips-next. I hope you can share the tests so your work doesn't bitrot with time (in particular when a good soul converts it to decodetree). Regards, Phil.