From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40AB6C432C1 for ; Tue, 24 Sep 2019 15:49:59 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 11696214AF for ; Tue, 24 Sep 2019 15:49:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 11696214AF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:47436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCn4f-0000hh-Oi for qemu-devel@archiver.kernel.org; Tue, 24 Sep 2019 11:49:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45430) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCmOP-0000jA-6T for qemu-devel@nongnu.org; Tue, 24 Sep 2019 11:06:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCmON-0005ht-Nl for qemu-devel@nongnu.org; Tue, 24 Sep 2019 11:06:17 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34452) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iCmOK-0005fo-Gm; Tue, 24 Sep 2019 11:06:12 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8EA4C18C4288; Tue, 24 Sep 2019 15:06:11 +0000 (UTC) Received: from [10.36.116.30] (ovpn-116-30.ams2.redhat.com [10.36.116.30]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9AF8A5D713; Tue, 24 Sep 2019 15:06:07 +0000 (UTC) Subject: Re: [PATCH v4 3/9] target/arm: Allow SVE to be disabled via a CPU property To: Andrew Jones , qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20190924113105.19076-1-drjones@redhat.com> <20190924113105.19076-4-drjones@redhat.com> From: Auger Eric Message-ID: <78300b0a-cb7e-ab08-ec65-92227feeb873@redhat.com> Date: Tue, 24 Sep 2019 17:06:05 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <20190924113105.19076-4-drjones@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.62]); Tue, 24 Sep 2019 15:06:11 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, armbru@redhat.com, imammedo@redhat.com, alex.bennee@linaro.org, Dave.Martin@arm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Drew, On 9/24/19 1:30 PM, Andrew Jones wrote: > Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via > a CPU property") we can disable the 'max' cpu model's VFP and neon > features, but there's no way to disable SVE. Add the 'sve=on|off' > property to give it that flexibility. We also rename > cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them > to follow the typical *_get/set_ pattern. > > Signed-off-by: Andrew Jones > Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Eric > --- > target/arm/cpu.c | 3 ++- > target/arm/cpu64.c | 42 ++++++++++++++++++++++++++++++++++------ > target/arm/monitor.c | 2 +- > tests/arm-cpu-features.c | 1 + > 4 files changed, 40 insertions(+), 8 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 2399c144718d..73be2ebfdd39 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -200,7 +200,8 @@ static void arm_cpu_reset(CPUState *s) > env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); > env->cp15.cptr_el[3] |= CPTR_EZ; > /* with maximum vector length */ > - env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; > + env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ? > + cpu->sve_max_vq - 1 : 0; > env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; > env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; > /* > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index d7f5bf610a7d..8cdb0c79fa7a 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -256,15 +256,15 @@ static void aarch64_a72_initfn(Object *obj) > define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); > } > > -static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, > - void *opaque, Error **errp) > +static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > { > ARMCPU *cpu = ARM_CPU(obj); > visit_type_uint32(v, name, &cpu->sve_max_vq, errp); > } > > -static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, > - void *opaque, Error **errp) > +static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > { > ARMCPU *cpu = ARM_CPU(obj); > Error *err = NULL; > @@ -279,6 +279,34 @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, > error_propagate(errp, err); > } > > +static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + ARMCPU *cpu = ARM_CPU(obj); > + bool value = cpu_isar_feature(aa64_sve, cpu); > + > + visit_type_bool(v, name, &value, errp); > +} > + > +static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + ARMCPU *cpu = ARM_CPU(obj); > + Error *err = NULL; > + bool value; > + uint64_t t; > + > + visit_type_bool(v, name, &value, &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > + > + t = cpu->isar.id_aa64pfr0;> + t = FIELD_DP64(t, ID_AA64PFR0, SVE, value); > + cpu->isar.id_aa64pfr0 = t; > +} > + > /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); > * otherwise, a CPU with as many features enabled as our emulation supports. > * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; > @@ -391,8 +419,10 @@ static void aarch64_max_initfn(Object *obj) > #endif > > cpu->sve_max_vq = ARM_MAX_VQ; > - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq, > - cpu_max_set_sve_vq, NULL, NULL, &error_fatal); > + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, > + cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal); > + object_property_add(obj, "sve", "bool", cpu_arm_get_sve, > + cpu_arm_set_sve, NULL, NULL, &error_fatal); > } > } > > diff --git a/target/arm/monitor.c b/target/arm/monitor.c > index edca8aa885f0..4fddb6c252a3 100644 > --- a/target/arm/monitor.c > +++ b/target/arm/monitor.c > @@ -97,7 +97,7 @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp) > * then the order that considers those dependencies must be used. > */ > static const char *cpu_model_advertised_features[] = { > - "aarch64", "pmu", > + "aarch64", "pmu", "sve", > NULL > }; > > diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c > index 198ff6d6b495..202bc0e3e823 100644 > --- a/tests/arm-cpu-features.c > +++ b/tests/arm-cpu-features.c > @@ -179,6 +179,7 @@ static void test_query_cpu_model_expansion(const void *data) > > if (g_str_equal(qtest_get_arch(), "aarch64")) { > assert_has_feature(qts, "max", "aarch64"); > + assert_has_feature(qts, "max", "sve"); > assert_has_feature(qts, "cortex-a57", "pmu"); > assert_has_feature(qts, "cortex-a57", "aarch64"); > >