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([2602:47:d49d:ec01:986f:cb56:6709:4057]) by smtp.gmail.com with ESMTPSA id c8-20020a170902d48800b001786b712f0esm4501838plg.227.2022.09.28.19.16.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Sep 2022 19:16:59 -0700 (PDT) Message-ID: <788dbfca-75ae-154d-f4ff-c1abeb3adef7@linaro.org> Date: Wed, 28 Sep 2022 19:16:57 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v5 00/17] tcg: CPUTLBEntryFull and TARGET_TB_PCREL Content-Language: en-US From: Richard Henderson To: qemu-devel@nongnu.org References: <20220925105124.82033-1-richard.henderson@linaro.org> Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20220925105124.82033-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.319, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/25/22 03:51, Richard Henderson wrote: > Smooshing these two patch sets back together for review bandwidth. > I hope to make this the next tcg-next pull. > > There are three from the first half, tlbentryfull, which are new. > These are following a hallway conversation with Peter about bits > in MemTxAttrs that are not actually related to memory transactions, > and infrastructure to address a to-do in an Arm patch set. > > There are a few patches from the second half, pcrel, that have not > been reviewed. > > 07-target-sparc-Use-tlb_set_page_full.patch > 08-accel-tcg-Move-byte_swap-from-MemTxAttrs-to-CPUTL.patch > 09-accel-tcg-Add-force_aligned-to-CPUTLBEntryFull.patch > 10-accel-tcg-Remove-PageDesc-code_bitmap.patch > 13-accel-tcg-Do-not-align-tb-page_addr-0.patch > 15-accel-tcg-Introduce-tb_pc-and-tb_pc_log.patch > 16-accel-tcg-Introduce-TARGET_TB_PCREL.patch FWIW, the target/sparc patch fails (the peril of insufficiently tested airport updates), so I'm going to drop 7+8 until I have time to investigate. I'm also going to drop patch 9 for now, and present it alongside the Arm patch that will use it. But otherwise, gentle ping. r~