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Wed, 02 Jul 2025 11:15:10 -0700 (PDT) Received: from [10.225.72.227] ([187.210.107.189]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-611b85c84afsm1777352eaf.40.2025.07.02.11.15.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Jul 2025 11:15:09 -0700 (PDT) Message-ID: <78bb2fc1-bdd5-43b1-83a8-b4e3a37d1825@linaro.org> Date: Wed, 2 Jul 2025 12:15:02 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 06/10] target/arm: Disable FEAT_F64MM if maximum SVE vector size too small From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org References: <20250702122213.758588-1-richard.henderson@linaro.org> <20250702122213.758588-7-richard.henderson@linaro.org> Content-Language: en-US In-Reply-To: <20250702122213.758588-7-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/2/25 06:22, Richard Henderson wrote: > All F64MM instructions operate on a 256-bit vector. > If only 128-bit vectors is supported by the cpu, > then the cpu cannot enable F64MM. > > Suggested-by: Peter Maydell > Signed-off-by: Richard Henderson > --- > target/arm/cpu64.c | 6 ++++++ > 1 file changed, 6 insertions(+) Ho hum. The idregs reorg landed overnight. I will update my branch, but will not re-post right away. r~ > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 200da1c489..c5c289eadf 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -237,6 +237,12 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) > /* From now on sve_max_vq is the actual maximum supported length. */ > cpu->sve_max_vq = max_vq; > cpu->sve_vq.map = vq_map; > + > + /* FEAT_F64MM requires the existence of a 256-bit vector size. */ > + if (max_vq < 2) { > + cpu->isar.id_aa64zfr0 = FIELD_DP64(cpu->isar.id_aa64zfr0, > + ID_AA64ZFR0, F64MM, 0); > + } > } > > /*