From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 14/16] target/arm: Implement ESB instruction
Date: Mon, 11 Apr 2022 15:14:53 -0700 [thread overview]
Message-ID: <78faaf43-4304-ff1e-1c8a-0102725eecbf@linaro.org> (raw)
In-Reply-To: <CAFEAcA_9Eu-WZn_yMhjj23GRkz14huEVSb8xckvRyygDngwXEQ@mail.gmail.com>
On 4/11/22 09:18, Peter Maydell wrote:
>> + ESB ---- 0011 0010 0000 1111 ---- 0001 0000
>> + ]
>
> Why don't we decode bits [11:8] here? I see it's the same
> as YIELD/WFE/WFI, but I'm not sure why we're not decoding
> those bits in those insns either...
See page F4-7074 in H.a, where bits [11:8] of the imm12 field are described with 'xxxx'.
>> +static bool trans_ESB(DisasContext *s, arg_ESB *a)
>> +{
>> + if (dc_isar_feature(aa32_ras, s) &&
>> + arm_dc_feature(s, ARM_FEATURE_EL2) &&
>> + s->current_el <= 1) {
>
> This is doing the right thing for M-profile but only rather
> indirectly because it happens to get caught by the FEATURE_EL2
> check.
Yes, I had though that a feature, reducing the number of checks, but...
> I think it would be safer to explicitly check for
> not-M-profile (which then gives you a place to put the
> "For M-profile minimal-RAS ESB can be a NOP" comment that got
> removed above).
... fair enough.
> I think a comment noting that without RAS we must NOP would
> be useful here.
Ok.
r~
next prev parent reply other threads:[~2022-04-11 22:16 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-09 0:07 [PATCH 00/16] target/arm: Implement features Debugv8p4, RAS, IESB Richard Henderson
2022-04-09 0:07 ` [PATCH 01/16] target/arm: Add isar predicates for FEAT_Debugv8p2 Richard Henderson
2022-04-11 12:33 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 02/16] target/arm: Adjust definition of CONTEXTIDR_EL2 Richard Henderson
2022-04-11 12:34 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 03/16] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Richard Henderson
2022-04-11 15:37 ` Peter Maydell
2022-04-11 16:28 ` Richard Henderson
2022-04-09 0:07 ` [PATCH 04/16] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Richard Henderson
2022-04-11 12:36 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 05/16] target/arm: Split out arm32_max_features Richard Henderson
2022-04-11 12:52 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 06/16] target/arm: Annotate arm_max_initfn with FEAT identifiers Richard Henderson
2022-04-11 12:55 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 07/16] target/arm: Use field names for manipulating EL2 and EL3 modes Richard Henderson
2022-04-11 12:56 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 08/16] target/arm: Enable FEAT_Debugv8p2 for -cpu max Richard Henderson
2022-04-11 13:09 ` Peter Maydell
2022-04-11 17:48 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 09/16] target/arm: Enable FEAT_Debugv8p4 " Richard Henderson
2022-04-11 13:27 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 10/16] target/arm: Add isar_feature_{aa64,any}_ras Richard Henderson
2022-04-11 13:29 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 11/16] target/arm: Add minimal RAS registers Richard Henderson
2022-04-11 15:49 ` Peter Maydell
2022-04-11 21:25 ` Richard Henderson
2022-04-09 0:07 ` [PATCH 12/16] target/arm: Enable SCR and HCR bits for RAS Richard Henderson
2022-04-11 15:50 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 13/16] target/arm: Implement virtual SError exceptions Richard Henderson
2022-04-11 16:00 ` Peter Maydell
2022-04-11 16:32 ` Peter Maydell
2022-04-11 21:42 ` Richard Henderson
2022-04-09 0:07 ` [PATCH 14/16] target/arm: Implement ESB instruction Richard Henderson
2022-04-11 16:18 ` Peter Maydell
2022-04-11 22:14 ` Richard Henderson [this message]
2022-04-12 9:56 ` Peter Maydell
2022-04-12 14:31 ` Richard Henderson
2022-04-09 0:07 ` [PATCH 15/16] target/arm: Enable FEAT_RAS for -cpu max Richard Henderson
2022-04-11 16:32 ` Peter Maydell
2022-04-09 0:07 ` [PATCH 16/16] target/arm: Enable FEAT_IESB " Richard Henderson
2022-04-11 16:33 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=78faaf43-4304-ff1e-1c8a-0102725eecbf@linaro.org \
--to=richard.henderson@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).