From: Richard Henderson <richard.henderson@linaro.org>
To: Deepak Gupta <debug@rivosinc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, pbonzini@redhat.com,
jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v4 13/16] target/riscv: compressed encodings for sspush and sspopchk
Date: Fri, 16 Aug 2024 15:09:10 +1000 [thread overview]
Message-ID: <794021c3-02f2-4b64-8d1c-a56125e09462@linaro.org> (raw)
In-Reply-To: <20240816010711.3055425-14-debug@rivosinc.com>
On 8/16/24 11:07, Deepak Gupta wrote:
> sspush/sspopchk have compressed encodings carved out of zcmops.
> compressed sspush is designated as c.mop.1 while compressed sspopchk
> is designated as c.mop.5.
>
> Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly
> c.sspopchk x5 exists while c.sspopchk x1 doesn't.
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> Co-developed-by: Jim Shu <jim.shu@sifive.com>
> Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
> ---
> target/riscv/insn16.decode | 2 ++
> target/riscv/insn_trans/trans_rvzicfiss.c.inc | 12 ++++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
> index 3953bcf82d..3b84a36233 100644
> --- a/target/riscv/insn16.decode
> +++ b/target/riscv/insn16.decode
> @@ -140,6 +140,8 @@ sw 110 ... ... .. ... 00 @cs_w
> addi 000 . ..... ..... 01 @ci
> addi 010 . ..... ..... 01 @c_li
> {
> + c_sspush 011 0 00001 00000 01 rs2=1 rs1=0 # c.sspush x1 carving out of zcmops
> + c_sspopchk 011 0 00101 00000 01 rs1=5 rd=0 # c.sspopchk x5 carving out of zcmops
> c_mop_n 011 0 0 n:3 1 00000 01
> illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
> addi 011 . 00010 ..... 01 @c_addi16sp
> diff --git a/target/riscv/insn_trans/trans_rvzicfiss.c.inc b/target/riscv/insn_trans/trans_rvzicfiss.c.inc
> index 05d439c1f6..67f5c7804a 100644
> --- a/target/riscv/insn_trans/trans_rvzicfiss.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzicfiss.c.inc
> @@ -109,3 +109,15 @@ static bool trans_sspush(DisasContext *ctx, arg_sspush *a)
> {
> return gen_sspush(ctx, a->rs2);
> }
> +
> +static bool trans_c_sspopchk(DisasContext *ctx, arg_c_sspopchk *a)
> +{
> + assert(a->rs1 == 5);
> + return gen_sspopchk(ctx, a->rs1);
> +}
> +
> +static bool trans_c_sspush(DisasContext *ctx, arg_c_sspush *a)
> +{
> + assert(a->rs2 == 1);
> + return gen_sspush(ctx, a->rs2);
> +}
This indirection is pointless. Have the decoder invoke the proper insn in the first
place. Identically with how we're treating 'addi', for instance.
r~
next prev parent reply other threads:[~2024-08-16 5:10 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-16 1:06 [PATCH v4 00/16] riscv support for control flow integrity extensions Deepak Gupta
2024-08-16 1:06 ` [PATCH v4 01/16] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-16 1:06 ` [PATCH v4 02/16] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-16 2:56 ` Richard Henderson
2024-08-16 1:06 ` [PATCH v4 03/16] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-16 2:59 ` Richard Henderson
2024-08-16 6:45 ` Deepak Gupta
2024-08-16 1:06 ` [PATCH v4 04/16] target/riscv: additional code information for sw check Deepak Gupta
2024-08-16 1:06 ` [PATCH v4 05/16] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-16 3:41 ` Richard Henderson
2024-08-16 6:49 ` Deepak Gupta
2024-08-16 1:07 ` [PATCH v4 06/16] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-16 3:59 ` Richard Henderson
2024-08-16 1:07 ` [PATCH v4 07/16] disas/riscv: enabled `lpad` disassembly Deepak Gupta
2024-08-16 4:00 ` Richard Henderson
2024-08-16 1:07 ` [PATCH v4 08/16] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-16 1:07 ` [PATCH v4 09/16] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-16 1:07 ` [PATCH v4 10/16] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-16 1:07 ` [PATCH v4 11/16] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-16 5:35 ` Richard Henderson
2024-08-16 1:07 ` [PATCH v4 12/16] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-16 5:43 ` Richard Henderson
2024-08-16 1:07 ` [PATCH v4 13/16] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-16 5:09 ` Richard Henderson [this message]
2024-08-16 6:56 ` Deepak Gupta
2024-08-16 7:28 ` Richard Henderson
2024-08-16 1:07 ` [PATCH v4 14/16] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-16 1:07 ` [PATCH v4 15/16] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-16 1:07 ` [PATCH v4 16/16] target/riscv: add trace-hooks for each case of sw-check exception Deepak Gupta
2024-08-16 5:52 ` Richard Henderson
2024-08-16 7:06 ` Deepak Gupta
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