From: "Cédric Le Goater" <clg@kaod.org>
To: <qemu-ppc@nongnu.org>, <qemu-devel@nongnu.org>
Subject: Re: [PATCH] target/ppc: Add extra float instructions to POWER5P processors
Date: Wed, 12 Jan 2022 12:38:02 +0100 [thread overview]
Message-ID: <794bd31d-8039-cf0f-e9b8-8bc285754cc9@kaod.org> (raw)
In-Reply-To: <20220110161959.758997-1-clg@kaod.org>
On 1/10/22 17:19, Cédric Le Goater wrote:
> ISA v2.03 introduced Floating Round to Integer instructions : frin,
> friz, frip, and frim. Add them to POWER5+.
>
> The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
> Estimate) instruction which was introduced in ISA v2.0x. The
> architecture document says its optional and that might the reason why
> it has been kept under the PPC_FLOAT_EXT. This means 970 CPUs can not
> use it under QEMU.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Applied to ppc7.0.
Thanks,
C.
prev parent reply other threads:[~2022-01-12 11:54 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-10 16:19 [PATCH] target/ppc: Add extra float instructions to POWER5P processors Cédric Le Goater
2022-01-10 18:42 ` BALATON Zoltan
2022-01-10 19:28 ` Cédric Le Goater
2022-01-12 11:38 ` Cédric Le Goater [this message]
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