Re: [Qemu-devel] [PATCH 1/9] target/ppc: Fix xvxsigdp

["Philippe Mathieu-Daudé" <f4bug@amsat.org>]

On 5/7/19 2:48 AM, Anton Blanchard wrote:
> Fix a typo in xvxsigdp where we put both results into the lower
> doubleword.
> 
> Fixes: dd977e4f45cb ("target/ppc: Optimize x[sv]xsigdp using deposit_i64()")
> Signed-off-by: Anton Blanchard <anton@ozlabs.org>
> ---
>  target/ppc/translate/vsx-impl.inc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
> index 11d9b75d01..4d8ca7cf32 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1820,7 +1820,7 @@ static void gen_xvxsigdp(DisasContext *ctx)
>      tcg_gen_movi_i64(t0, 0x0010000000000000);
>      tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
>      tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
> -    tcg_gen_deposit_i64(xth, t0, xbl, 0, 52);
> +    tcg_gen_deposit_i64(xtl, t0, xbl, 0, 52);

Argh I'm very sorry. I obviously failed while copy/pasting

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

>      set_cpu_vsrl(xT(ctx->opcode), xtl);
>  
>      tcg_temp_free_i64(t0);
>