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[88.21.103.193]) by smtp.gmail.com with ESMTPSA id y184sm13621904wmg.7.2019.05.07.01.01.29 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Tue, 07 May 2019 01:01:30 -0700 (PDT) To: Anton Blanchard , qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20190507004811.29968-1-anton@ozlabs.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: url=http://pgp.mit.edu/pks/lookup?op=get&search=0xE3E32C2CDEADC0DE Message-ID: <79aadb7c-52a0-34e4-dbd3-8e40a7203862@amsat.org> Date: Tue, 7 May 2019 10:01:28 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190507004811.29968-1-anton@ozlabs.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: Re: [Qemu-devel] [PATCH 1/9] target/ppc: Fix xvxsigdp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com, mark.cave-ayland@ilande.co.uk, sandipandas1990@gmail.com, richard.henderson@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/7/19 2:48 AM, Anton Blanchard wrote: > Fix a typo in xvxsigdp where we put both results into the lower > doubleword. > > Fixes: dd977e4f45cb ("target/ppc: Optimize x[sv]xsigdp using deposit_i64()") > Signed-off-by: Anton Blanchard > --- > target/ppc/translate/vsx-impl.inc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c > index 11d9b75d01..4d8ca7cf32 100644 > --- a/target/ppc/translate/vsx-impl.inc.c > +++ b/target/ppc/translate/vsx-impl.inc.c > @@ -1820,7 +1820,7 @@ static void gen_xvxsigdp(DisasContext *ctx) > tcg_gen_movi_i64(t0, 0x0010000000000000); > tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); > tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); > - tcg_gen_deposit_i64(xth, t0, xbl, 0, 52); > + tcg_gen_deposit_i64(xtl, t0, xbl, 0, 52); Argh I'm very sorry. I obviously failed while copy/pasting Reviewed-by: Philippe Mathieu-Daudé > set_cpu_vsrl(xT(ctx->opcode), xtl); > > tcg_temp_free_i64(t0); >