qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: Xiaojuan Yang <yangxiaojuan@loongson.cn>, qemu-devel@nongnu.org
Cc: gaosong@loongson.cn, mark.cave-ayland@ilande.co.uk,
	mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca
Subject: Re: [PATCH v4 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
Date: Wed, 18 May 2022 11:04:20 -0700	[thread overview]
Message-ID: <79bbbf79-a019-17f4-9008-f57a8c375fcb@linaro.org> (raw)
In-Reply-To: <20220517113023.3051143-35-yangxiaojuan@loongson.cn>

On 5/17/22 04:30, Xiaojuan Yang wrote:
> +static void extioi_update_irq(LoongArchExtIOI *s, int irq_num, int level)
> +{
> +    int ipnum, cpu, found, irq_index, irq_mask;
> +
> +    ipnum = get_ipmap(s, irq_num);
> +    cpu = get_coremap(s, irq_num);
> +    irq_index = irq_num / 32;
> +    irq_mask = 1 << (irq_num & 0x1f);
> +
> +    if (level) {
> +        /* if not enable return false */
> +        if (((s->enable[irq_index]) & irq_mask) == 0) {
> +            s->sw_pending[irq_index] |= irq_mask;
> +            return;
> +        }
> +        s->coreisr[cpu][irq_index] |= irq_mask;
> +        found = find_first_bit(s->sw_isr[cpu][ipnum], EXTIOI_IRQS);

AGAIN!  You CANNOT use only part of the bitmap.h interface.

>> +    uint64_t sw_isr[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP][EXTIOI_IRQS / 64];

This has not been declared with DECLARE_BITMAP, therefore you will see a compile-time 
error when building on an ILP32 (i686) or P64 (win64) host.

I pointed this out to you as recently as v2 of this series.
I am really disappointed to see this regress in just one month.

You can test this yourself with

   IMAGES='fedora-i386-cross fedora-win32-cross fedora-win64-cross' \
   make docker-test-build

Please do so before your next submission.

> +static void extioi_writew(void *opaque, hwaddr addr,
> +                          uint64_t val, unsigned size)
> +{
> +    LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
> +    int i, cpu, index, old_data, data_offset;
> +    int old_ip, new_ip, old_core, new_core, irq_mask, irq_num;
> +    uint32_t offset;
> +    int old_ipnum[128], old_cpu[4];
> +    trace_loongarch_extioi_writew(size, (uint32_t)addr, val);
> +
> +    offset = addr & 0xffff;
> +
> +    switch (offset) {
> +    case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
> +        index = (offset - EXTIOI_NODETYPE_START) >> 2;
> +        s->nodetype[index] = val;
> +        break;
> +    case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
> +        /* get irq number */
> +        offset -= EXTIOI_IPMAP_START;
> +        index = offset >> 2;
> +        /*
> +         * 4 bytes writing, set 4 irq groups one time,
> +         * and one group is 32 irqs, so set 128 irqs mapping
> +         */
> +        for (i = 0; i < 128; i++) {
> +            old_ipnum[i] = get_ipmap(s, offset);
> +            offset += 1;
> +        }

You increment offset in the first loop,

> +        s->ipmap[index] = val;
> +        offset -= 128;
> +        /* if core isr is set, need to update irq */
> +        for (i = 0; i < 128; i++) {
> +            old_ip = old_ipnum[i];
> +            new_ip = get_ipmap(s, offset);
> +            cpu = get_coremap(s, offset);
> +            if (old_ip != new_ip) {
> +                if (s->coreisr[cpu][offset / 32] & (1 << (offset & 0x1f))) {
> +                    extioi_update_irq(s, offset, 1);
> +                }
> +            }
> +        }

but not the second.

> +    case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
> +        index = (offset - EXTIOI_ENABLE_START) >> 2;
> +        old_data = s->enable[index];
> +        if (old_data != (int)val) {
> +            s->enable[index] = val;
> +            /* get data diff */
> +            old_data ^= val;
> +            /* value change from 0 to 1 */
> +            old_data &= val;
> +            data_offset = ctz32(old_data);
> +            while (data_offset != 32) {
> +                /*
> +                 * enable bit change from 0 to 1,
> +                 * need to update irq by pending bits
> +                 */
> +                irq_num = data_offset + index * 32;
> +                irq_mask = 1 << data_offset;
> +                if (s->sw_pending[index] & irq_mask) {
> +                    extioi_update_irq(s, irq_num, 1);
> +                    s->sw_pending[index] &= ~irq_mask;
> +                }
> +                old_data &= ~irq_mask;
> +                data_offset = ctz32(old_data);
> +            }

I'm still not convinced.  Why would unmasking (enabling) an irq call update_irq, but 
masking (disabling) the same irq not also call update_irq?

Even if that is correct, the testing of sw_pending could be done in parallel, like

     old_data &= s->sw_pending[index];

before the loop, instead of testing each bit one at a time within the loop.

The loop itself should be written

	while (old_data) {
	    data_offset = ctz32(old_data);
             ...
             old_data &= old_data - 1;
         }

so that you don't bother computing ctz for zero values, and with the adjustment to 
old_data before the loop, you don't need irq_mask within the loop.

Likewise with the updates to COREISR and COREMAP.


r~


  reply	other threads:[~2022-05-18 18:06 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-17 11:29 [PATCH v4 00/43] Add LoongArch softmmu support Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 01/43] target/loongarch: Add README Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 02/43] target/loongarch: Add core definition Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 03/43] target/loongarch: Add main translation routines Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 04/43] target/loongarch: Add fixed point arithmetic instruction translation Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 05/43] target/loongarch: Add fixed point shift " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 06/43] target/loongarch: Add fixed point bit " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 07/43] target/loongarch: Add fixed point load/store " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 08/43] target/loongarch: Add fixed point atomic " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 09/43] target/loongarch: Add fixed point extra " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 10/43] target/loongarch: Add floating point arithmetic " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 11/43] target/loongarch: Add floating point comparison " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 12/43] target/loongarch: Add floating point conversion " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 13/43] target/loongarch: Add floating point move " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 14/43] target/loongarch: Add floating point load/store " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 15/43] target/loongarch: Add branch " Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 16/43] target/loongarch: Add disassembler Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 17/43] target/loongarch: Add target build suport Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 18/43] target/loongarch: Add system emulation introduction Xiaojuan Yang
2022-05-17 11:29 ` [PATCH v4 19/43] target/loongarch: Add CSRs definition Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 20/43] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 21/43] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 22/43] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 23/43] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 24/43] target/loongarch: Add constant timer support Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 25/43] target/loongarch: Add LoongArch CSR instruction Xiaojuan Yang
2022-05-18 17:18   ` Richard Henderson
2022-05-17 11:30 ` [PATCH v4 26/43] target/loongarch: Add LoongArch IOCSR instruction Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 27/43] target/loongarch: Add TLB instruction support Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 28/43] target/loongarch: Add other core instructions support Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 29/43] target/loongarch: Add timer related " Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 30/43] hw/loongarch: Add support loongson3 virt machine type Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
2022-05-18 18:04   ` Richard Henderson [this message]
2022-05-19  3:03     ` yangxiaojuan
2022-05-17 11:30 ` [PATCH v4 35/43] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 36/43] Enable common virtio pci support for LoongArch Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 37/43] hw/loongarch: Add some devices support for 3A5000 Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 38/43] hw/loongarch: Add LoongArch ls7a rtc device support Xiaojuan Yang
2022-05-18 19:59   ` Richard Henderson
2022-05-19 13:04     ` yangxiaojuan
2022-05-19 15:24       ` Richard Henderson
2022-05-20 10:07         ` yangxiaojuan
2022-05-17 11:30 ` [PATCH v4 39/43] hw/loongarch: Add LoongArch load elf function Xiaojuan Yang
2022-05-18 20:01   ` Richard Henderson
2022-05-17 11:30 ` [PATCH v4 40/43] hw/loongarch: Add LoongArch ls7a acpi device support Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 41/43] target/loongarch: Add gdb support Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system Xiaojuan Yang
2022-05-17 11:30 ` [PATCH v4 43/43] target/loongarch: 'make check-tcg' support Xiaojuan Yang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=79bbbf79-a019-17f4-9008-f57a8c375fcb@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=ani@anisinha.ca \
    --cc=gaosong@loongson.cn \
    --cc=imammedo@redhat.com \
    --cc=mark.cave-ayland@ilande.co.uk \
    --cc=mst@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=yangxiaojuan@loongson.cn \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).