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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7c53df21c89sm706935085a.38.2025.03.12.09.07.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 09:07:49 -0700 (PDT) Message-ID: <79bcc36c-1a12-4b18-a54c-afe734d6bef0@redhat.com> Date: Wed, 12 Mar 2025 17:07:44 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 05/20] hw/arm/smmuv3-accel: Associate a pxb-pcie bus Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> <20250311141045.66620-6-shameerali.kolothum.thodi@huawei.com> From: Eric Auger In-Reply-To: <20250311141045.66620-6-shameerali.kolothum.thodi@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Shameer, On 3/11/25 3:10 PM, Shameer Kolothum wrote: > User must associate a pxb-pcie root bus to smmuv3-accel > and that is set as the primary-bus for the smmu dev. why do we require a pxb-pcie root bus? why can't pci.0 root bus be used for simpler use cases (ie. I just want to passthough a NIC in accelerated mode). Or may pci.0 is also called a pax-pcie root bus? Besides, why do we put the constraint to plug on a root bus. I know that at this point we always plug to pci.0 but with the new -device option it would be possible to plug it anywhere in the pcie hierarchy. At SOC level can't an SMMU be plugged anywhere protecting just a few RIDs? > > Signed-off-by: Shameer Kolothum > --- > hw/arm/smmuv3-accel.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index c327661636..1471b65374 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -9,6 +9,21 @@ > #include "qemu/osdep.h" > > #include "hw/arm/smmuv3-accel.h" > +#include "hw/pci/pci_bridge.h" > + > +static int smmuv3_accel_pxb_pcie_bus(Object *obj, void *opaque) > +{ > + DeviceState *d = opaque; > + > + if (object_dynamic_cast(obj, "pxb-pcie-bus")) { > + PCIBus *bus = PCI_HOST_BRIDGE(obj->parent)->bus; > + if (d->parent_bus && !strcmp(bus->qbus.name, d->parent_bus->name)) { > + object_property_set_link(OBJECT(d), "primary-bus", OBJECT(bus), > + &error_abort); if you want to stop the recursive search I think you need to return something != 0 here. I don't really understand why we don't simply set the primary-bus to where -device arm-smmuv3-accel, bus=? or maybe enforce that this bus is an actual root bus if we really need that? > + } > + } > + return 0; > +} > > static void smmu_accel_realize(DeviceState *d, Error **errp) > { > @@ -17,6 +32,9 @@ static void smmu_accel_realize(DeviceState *d, Error **errp) > SysBusDevice *dev = SYS_BUS_DEVICE(d); > Error *local_err = NULL; > > + object_child_foreach_recursive(object_get_root(), > + smmuv3_accel_pxb_pcie_bus, d); > + > object_property_set_bool(OBJECT(dev), "accel", true, &error_abort); > c->parent_realize(d, &local_err); > if (local_err) { > @@ -33,6 +51,7 @@ static void smmuv3_accel_class_init(ObjectClass *klass, void *data) > device_class_set_parent_realize(dc, smmu_accel_realize, > &c->parent_realize); > dc->hotpluggable = false; > + dc->bus_type = TYPE_PCIE_BUS; shouldn't it below to 3/20? It is not really related to primary_bus setting? Thanks Eric > } > > static const TypeInfo smmuv3_accel_type_info = {