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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v2 18/25] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , David Gibson , Greg Kurz , qemu-ppc@nongnu.org References: <20230307183503.2512684-1-richard.henderson@linaro.org> <20230307183503.2512684-19-richard.henderson@linaro.org> From: Daniel Henrique Barboza In-Reply-To: <20230307183503.2512684-19-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/7/23 15:34, Richard Henderson wrote: > All uses are strictly read-only. > > Signed-off-by: Richard Henderson > --- Reviewed-by: Daniel Henrique Barboza > Cc: Daniel Henrique Barboza > Cc: Cédric Le Goater > Cc: David Gibson > Cc: Greg Kurz > Cc: qemu-ppc@nongnu.org > --- > target/ppc/translate/fp-impl.c.inc | 26 ++++++++++++-------------- > 1 file changed, 12 insertions(+), 14 deletions(-) > > diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc > index d5d88e7d49..57d8437851 100644 > --- a/target/ppc/translate/fp-impl.c.inc > +++ b/target/ppc/translate/fp-impl.c.inc > @@ -348,7 +348,7 @@ static void gen_fcmpo(DisasContext *ctx) > t0 = tcg_temp_new_i64(); > t1 = tcg_temp_new_i64(); > gen_reset_fpstatus(); > - crf = tcg_const_i32(crfD(ctx->opcode)); > + crf = tcg_constant_i32(crfD(ctx->opcode)); > get_fpr(t0, rA(ctx->opcode)); > get_fpr(t1, rB(ctx->opcode)); > gen_helper_fcmpo(cpu_env, t0, t1, crf); > @@ -368,7 +368,7 @@ static void gen_fcmpu(DisasContext *ctx) > t0 = tcg_temp_new_i64(); > t1 = tcg_temp_new_i64(); > gen_reset_fpstatus(); > - crf = tcg_const_i32(crfD(ctx->opcode)); > + crf = tcg_constant_i32(crfD(ctx->opcode)); > get_fpr(t0, rA(ctx->opcode)); > get_fpr(t1, rB(ctx->opcode)); > gen_helper_fcmpu(cpu_env, t0, t1, crf); > @@ -541,7 +541,7 @@ static void gen_mcrfs(DisasContext *ctx) > tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, > ~((0xF << shift) & FP_EX_CLEAR_BITS)); > /* FEX and VX need to be updated, so don't set fpscr directly */ > - tmask = tcg_const_i32(1 << nibble); > + tmask = tcg_constant_i32(1 << nibble); > gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask); > } > > @@ -681,9 +681,7 @@ static void gen_mtfsb0(DisasContext *ctx) > crb = 31 - crbD(ctx->opcode); > gen_reset_fpstatus(); > if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { > - TCGv_i32 t0; > - t0 = tcg_const_i32(crb); > - gen_helper_fpscr_clrbit(cpu_env, t0); > + gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb)); > } > if (unlikely(Rc(ctx->opcode) != 0)) { > tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); > @@ -703,9 +701,7 @@ static void gen_mtfsb1(DisasContext *ctx) > crb = 31 - crbD(ctx->opcode); > /* XXX: we pretend we can only do IEEE floating-point computations */ > if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { > - TCGv_i32 t0; > - t0 = tcg_const_i32(crb); > - gen_helper_fpscr_setbit(cpu_env, t0); > + gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb)); > } > if (unlikely(Rc(ctx->opcode) != 0)) { > tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); > @@ -733,10 +729,12 @@ static void gen_mtfsf(DisasContext *ctx) > gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); > return; > } > - if (l) { > - t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); > + if (!l) { > + t0 = tcg_constant_i32(flm << (w * 8)); > + } else if (ctx->insns_flags2 & PPC2_ISA205) { > + t0 = tcg_constant_i32(0xffff); > } else { > - t0 = tcg_const_i32(flm << (w * 8)); > + t0 = tcg_constant_i32(0xff); > } > t1 = tcg_temp_new_i64(); > get_fpr(t1, rB(ctx->opcode)); > @@ -767,8 +765,8 @@ static void gen_mtfsfi(DisasContext *ctx) > return; > } > sh = (8 * w) + 7 - bf; > - t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); > - t1 = tcg_const_i32(1 << sh); > + t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); > + t1 = tcg_constant_i32(1 << sh); > gen_helper_store_fpscr(cpu_env, t0, t1); > if (unlikely(Rc(ctx->opcode) != 0)) { > tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);