From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: "Inès Varhol" <ines.varhol@telecom-paris.fr>, qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Arnaud Minier <arnaud.minier@telecom-paris.fr>,
Alexandre Iooss <erdnaxe@crans.org>,
Paolo Bonzini <pbonzini@redhat.com>,
qemu-arm@nongnu.org, Alistair Francis <alistair@alistair23.me>,
Samuel Tardieu <sam@rfc1149.net>
Subject: Re: [PATCH v5 1/2] hw/arm: Add minimal support for the STM32L4x5 SoC
Date: Mon, 8 Jan 2024 13:09:37 +0100 [thread overview]
Message-ID: <7a19dcea-4e54-4347-9bc4-1122c41273d2@linaro.org> (raw)
In-Reply-To: <20240106163905.42027-2-ines.varhol@telecom-paris.fr>
Hi Inès,
On 6/1/24 17:38, Inès Varhol wrote:
> This patch adds a new STM32L4x5 SoC, it is necessary to add support for
> the B-L475E-IOT01A board.
> The implementation is derived from the STM32F405 SoC.
> The implementation contains no peripherals, only memory regions are
> implemented.
>
> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
> ---
> MAINTAINERS | 8 +
> hw/arm/Kconfig | 5 +
> hw/arm/meson.build | 1 +
> hw/arm/stm32l4x5_soc.c | 268 +++++++++++++++++++++++++++++++++
> include/hw/arm/stm32l4x5_soc.h | 57 +++++++
> 5 files changed, 339 insertions(+)
> create mode 100644 hw/arm/stm32l4x5_soc.c
> create mode 100644 include/hw/arm/stm32l4x5_soc.h
> +static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
> +{
> + ERRP_GUARD();
> + Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);
> + const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);
> + MemoryRegion *system_memory = get_system_memory();
> + DeviceState *armv7m;
> +
> + /*
> + * We use s->refclk internally and only define it with qdev_init_clock_in()
> + * so it is correctly parented and not leaked on an init/deinit; it is not
> + * intended as an externally exposed clock.
> + */
> + if (clock_has_source(s->refclk)) {
> + error_setg(errp, "refclk clock must not be wired up by the board code");
> + return;
> + }
> +
> + if (!clock_has_source(s->sysclk)) {
> + error_setg(errp, "sysclk clock must be wired up by the board code");
> + return;
> + }
> +
> + /*
> + * TODO: ideally we should model the SoC RCC and its ability to
> + * change the sysclk frequency and define different sysclk sources.
> + */
> +
> + /* The refclk always runs at frequency HCLK / 8 */
> + clock_set_mul_div(s->refclk, 8, 1);
> + clock_set_source(s->refclk, s->sysclk);
> +
> + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
> + sc->flash_size, errp);
> + if (*errp) {
> + return;
Since commit b9159451d3 ("memory: Have memory_region_init_rom
handler return a boolean") you don't need that anymore.
> + }
> + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
> + "flash_boot_alias", &s->flash, 0,
> + sc->flash_size);
> +
> + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
> + memory_region_add_subregion(system_memory, 0, &s->flash_alias);
> +
> + memory_region_init_ram(&s->sram1, OBJECT(dev_soc), "SRAM1", SRAM1_SIZE,
> + errp);
> + if (*errp) {
> + return;
Ditto with commit fe5f33d6b0 ("memory: Have memory_region_init_ram
handler return a boolean").
> + }
> + memory_region_add_subregion(system_memory, SRAM1_BASE_ADDRESS, &s->sram1);
> +
> + memory_region_init_ram(&s->sram2, OBJECT(dev_soc), "SRAM2", SRAM2_SIZE,
> + errp);
> + if (*errp) {
> + return;
Ditto.
Can be done as a cleanup patch on top if you don't have time to post
a v6 before Peter queue your v5.
> + }
> + memory_region_add_subregion(system_memory, SRAM2_BASE_ADDRESS, &s->sram2);
> +
> + object_initialize_child(OBJECT(dev_soc), "armv7m", &s->armv7m, TYPE_ARMV7M);
> + armv7m = DEVICE(&s->armv7m);
> + qdev_prop_set_uint32(armv7m, "num-irq", 96);
> + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
> + qdev_prop_set_bit(armv7m, "enable-bitband", true);
> + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> + qdev_connect_clock_in(armv7m, "refclk", s->refclk);
> + object_property_set_link(OBJECT(&s->armv7m), "memory",
> + OBJECT(system_memory), &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> + return;
> + }
> +
> + /* APB1 BUS */
> + create_unimplemented_device("TIM2", 0x40000000, 0x400);
> + create_unimplemented_device("TIM3", 0x40000400, 0x400);
> + create_unimplemented_device("TIM4", 0x40000800, 0x400);
> + create_unimplemented_device("TIM5", 0x40000C00, 0x400);
> + create_unimplemented_device("TIM6", 0x40001000, 0x400);
> + create_unimplemented_device("TIM7", 0x40001400, 0x400);
> + /* RESERVED: 0x40001800, 0x1000 */
> + create_unimplemented_device("RTC", 0x40002800, 0x400);
> + create_unimplemented_device("WWDG", 0x40002C00, 0x400);
> + create_unimplemented_device("IWDG", 0x40003000, 0x400);
> + /* RESERVED: 0x40001800, 0x400 */
> + create_unimplemented_device("SPI2", 0x40003800, 0x400);
> + create_unimplemented_device("SPI3", 0x40003C00, 0x400);
> + /* RESERVED: 0x40004000, 0x400 */
> + create_unimplemented_device("USART2", 0x40004400, 0x400);
> + create_unimplemented_device("USART3", 0x40004800, 0x400);
> + create_unimplemented_device("UART4", 0x40004C00, 0x400);
> + create_unimplemented_device("UART5", 0x40005000, 0x400);
> + create_unimplemented_device("I2C1", 0x40005400, 0x400);
> + create_unimplemented_device("I2C2", 0x40005800, 0x400);
> + create_unimplemented_device("I2C3", 0x40005C00, 0x400);
> + /* RESERVED: 0x40006000, 0x400 */
> + create_unimplemented_device("CAN1", 0x40006400, 0x400);
> + /* RESERVED: 0x40006800, 0x400 */
> + create_unimplemented_device("PWR", 0x40007000, 0x400);
> + create_unimplemented_device("DAC1", 0x40007400, 0x400);
> + create_unimplemented_device("OPAMP", 0x40007800, 0x400);
> + create_unimplemented_device("LPTIM1", 0x40007C00, 0x400);
> + create_unimplemented_device("LPUART1", 0x40008000, 0x400);
> + /* RESERVED: 0x40008400, 0x400 */
> + create_unimplemented_device("SWPMI1", 0x40008800, 0x400);
> + /* RESERVED: 0x40008C00, 0x800 */
> + create_unimplemented_device("LPTIM2", 0x40009400, 0x400);
> + /* RESERVED: 0x40009800, 0x6800 */
> +
> + /* APB2 BUS */
> + create_unimplemented_device("SYSCFG", 0x40010000, 0x30);
> + create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0);
> + create_unimplemented_device("COMP", 0x40010200, 0x200);
> + create_unimplemented_device("EXTI", 0x40010400, 0x400);
> + /* RESERVED: 0x40010800, 0x1400 */
> + create_unimplemented_device("FIREWALL", 0x40011C00, 0x400);
> + /* RESERVED: 0x40012000, 0x800 */
> + create_unimplemented_device("SDMMC1", 0x40012800, 0x400);
> + create_unimplemented_device("TIM1", 0x40012C00, 0x400);
> + create_unimplemented_device("SPI1", 0x40013000, 0x400);
> + create_unimplemented_device("TIM8", 0x40013400, 0x400);
> + create_unimplemented_device("USART1", 0x40013800, 0x400);
> + /* RESERVED: 0x40013C00, 0x400 */
> + create_unimplemented_device("TIM15", 0x40014000, 0x400);
> + create_unimplemented_device("TIM16", 0x40014400, 0x400);
> + create_unimplemented_device("TIM17", 0x40014800, 0x400);
> + /* RESERVED: 0x40014C00, 0x800 */
> + create_unimplemented_device("SAI1", 0x40015400, 0x400);
> + create_unimplemented_device("SAI2", 0x40015800, 0x400);
> + /* RESERVED: 0x40015C00, 0x400 */
> + create_unimplemented_device("DFSDM1", 0x40016000, 0x400);
> + /* RESERVED: 0x40016400, 0x9C00 */
> +
> + /* AHB1 BUS */
> + create_unimplemented_device("DMA1", 0x40020000, 0x400);
> + create_unimplemented_device("DMA2", 0x40020400, 0x400);
> + /* RESERVED: 0x40020800, 0x800 */
> + create_unimplemented_device("RCC", 0x40021000, 0x400);
> + /* RESERVED: 0x40021400, 0xC00 */
> + create_unimplemented_device("FLASH", 0x40022000, 0x400);
> + /* RESERVED: 0x40022400, 0xC00 */
> + create_unimplemented_device("CRC", 0x40023000, 0x400);
> + /* RESERVED: 0x40023400, 0x400 */
> + create_unimplemented_device("TSC", 0x40024000, 0x400);
> +
> + /* RESERVED: 0x40024400, 0x7FDBC00 */
> +
> + /* AHB2 BUS */
> + create_unimplemented_device("GPIOA", 0x48000000, 0x400);
> + create_unimplemented_device("GPIOB", 0x48000400, 0x400);
> + create_unimplemented_device("GPIOC", 0x48000800, 0x400);
> + create_unimplemented_device("GPIOD", 0x48000C00, 0x400);
> + create_unimplemented_device("GPIOE", 0x48001000, 0x400);
> + create_unimplemented_device("GPIOF", 0x48001400, 0x400);
> + create_unimplemented_device("GPIOG", 0x48001800, 0x400);
> + create_unimplemented_device("GPIOH", 0x48001C00, 0x400);
> + /* RESERVED: 0x48002000, 0x7FDBC00 */
> + create_unimplemented_device("OTG_FS", 0x50000000, 0x40000);
> + create_unimplemented_device("ADC", 0x50040000, 0x400);
> + /* RESERVED: 0x50040400, 0x20400 */
> + create_unimplemented_device("RNG", 0x50060800, 0x400);
> +
> + /* AHB3 BUS */
> + create_unimplemented_device("FMC", 0xA0000000, 0x1000);
> + create_unimplemented_device("QUADSPI", 0xA0001000, 0x400);
> +}
next prev parent reply other threads:[~2024-01-08 12:11 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-06 16:38 [PATCH v5 0/2] Add minimal support for the B-L475E-IOT01A board Inès Varhol
2024-01-06 16:38 ` [PATCH v5 1/2] hw/arm: Add minimal support for the STM32L4x5 SoC Inès Varhol
2024-01-08 12:09 ` Philippe Mathieu-Daudé [this message]
2024-01-06 16:38 ` [PATCH v5 2/2] hw/arm: Add minimal support for the B-L475E-IOT01A board Inès Varhol
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7a19dcea-4e54-4347-9bc4-1122c41273d2@linaro.org \
--to=philmd@linaro.org \
--cc=alistair@alistair23.me \
--cc=arnaud.minier@telecom-paris.fr \
--cc=erdnaxe@crans.org \
--cc=ines.varhol@telecom-paris.fr \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=sam@rfc1149.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).