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([2602:47:d49d:ec01:526e:3326:a84e:e5e3]) by smtp.gmail.com with ESMTPSA id e6-20020a170902ef4600b0016d1b70872asm547508plx.134.2022.10.04.14.09.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Oct 2022 14:09:44 -0700 (PDT) Message-ID: <7a2c6a64-87f7-fd8f-d406-6a0b50164f0b@linaro.org> Date: Tue, 4 Oct 2022 14:09:43 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v5 9/9] target/arm: Enable TARGET_TB_PCREL Content-Language: en-US From: Richard Henderson To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20220930220312.135327-1-richard.henderson@linaro.org> <20220930220312.135327-10-richard.henderson@linaro.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.449, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/4/22 12:27, Richard Henderson wrote: > On 10/4/22 09:23, Peter Maydell wrote: >>>   void arm_cpu_synchronize_from_tb(CPUState *cs, >>>                                    const TranslationBlock *tb) >>>   { >>> -    ARMCPU *cpu = ARM_CPU(cs); >>> -    CPUARMState *env = &cpu->env; >>> - >>> -    /* >>> -     * It's OK to look at env for the current mode here, because it's >>> -     * never possible for an AArch64 TB to chain to an AArch32 TB. >>> -     */ >>> -    if (is_a64(env)) { >>> -        env->pc = tb_pc(tb); >>> -    } else { >>> -        env->regs[15] = tb_pc(tb); >>> +    /* The program counter is always up to date with TARGET_TB_PCREL. */ >> >> I was confused for a bit about this, but it works because >> although the synchronize_from_tb hook has a name that implies >> it's comparatively general purpose, in fact we use it only >> in the special case of "we abandoned execution at the start of >> this TB without executing any of it". > > Correct. > >>> @@ -347,16 +354,22 @@ static void gen_exception_internal(int excp) >>> >>>   static void gen_exception_internal_insn(DisasContext *s, int excp) >>>   { >>> +    target_ulong pc_save = s->pc_save; >>> + >>>       gen_a64_update_pc(s, 0); >>>       gen_exception_internal(excp); >>>       s->base.is_jmp = DISAS_NORETURN; >>> +    s->pc_save = pc_save; >> >> What is trashing s->pc_save that we have to work around like this, >> here and in the other similar changes ? > > gen_a64_update_pc trashes pc_save. > > Off of the top of my head, I can't remember what conditionally uses exceptions (single > step?). Oh, duh, any conditional a32 instruction. To some extent this instance duplicates s->pc_cond_save, but the usage pattern there is brcond(..., s->condlabel); s->pc_cond_save = s->pc_save; gen_update_pc(s, 0); /* pc_save = pc_curr */ raise_exception; if (s->pc_cond_save != s->pc_save) { gen_update_pc(s->pc_save - s->pc_cond_save); } /* s->pc_save now matches the state at brcond */ condlabel: So, we have exited the TB via exception, and the second gen_update_pc would be deleted as dead code, it's just as easy to keep s->pc_save unchanged so that the second gen_update_pc is not emitted. We certainly *must* update s->pc_save around indirect branches, so that we don't wind up with an assert on s->pc_save != -1. r~