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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: peter.maydell@linaro.org,
	Richard Henderson <richard.henderson@linaro.org>
Cc: alex.bennee@linaro.org, qemu-devel@nongnu.org,
	mark.cave-ayland@ilande.co.uk, Max Filippov <jcmvbkbc@gmail.com>
Subject: Re: [PATCH for-6.1 v6 14/17] accel/tcg: Move breakpoint recognition outside translation
Date: Tue, 28 Nov 2023 12:08:37 +0100	[thread overview]
Message-ID: <7a6efb0c-62fb-4047-a20a-261ebb8c99ac@linaro.org> (raw)
In-Reply-To: <20210720195439.626594-15-richard.henderson@linaro.org>

Hi,

On 20/7/21 21:54, Richard Henderson wrote:
> Trigger breakpoints before beginning translation of a TB
> that would begin with a BP.  Thus we never generate code
> for the BP at all.
> 
> Single-step instructions within a page containing a BP so
> that we are sure to check each insn for the BP as above.
> 
> We no longer need to flush any TBs when changing BPs.
> 
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/286
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/404
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/489
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   accel/tcg/cpu-exec.c   | 91 ++++++++++++++++++++++++++++++++++++++++--
>   accel/tcg/translator.c | 24 +----------
>   cpu.c                  | 20 ----------
>   3 files changed, 89 insertions(+), 46 deletions(-)


> diff --git a/cpu.c b/cpu.c
> index 91d9e38acb..d6ae5ae581 100644
> --- a/cpu.c
> +++ b/cpu.c
> @@ -225,11 +225,6 @@ void tb_invalidate_phys_addr(target_ulong addr)
>       tb_invalidate_phys_page_range(addr, addr + 1);
>       mmap_unlock();
>   }
> -
> -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
> -{
> -    tb_invalidate_phys_addr(pc);
> -}

This patch removed the last use of tb_invalidate_phys_addr() in
user emulation:

   void tb_invalidate_phys_addr(hwaddr addr)
   {
       mmap_lock();
       tb_invalidate_phys_page(addr);
       mmap_unlock();
   }

Do we still need it?

(In sysemu there is a single use in Xtensa tb_invalidate_virtual_addr).

>   #else
>   void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
>   {
> @@ -250,17 +245,6 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
>       ram_addr = memory_region_get_ram_addr(mr) + addr;
>       tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
>   }
> -
> -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
> -{
> -    /*
> -     * There may not be a virtual to physical translation for the pc
> -     * right now, but there may exist cached TB for this pc.
> -     * Flush the whole TB cache to force re-translation of such TBs.
> -     * This is heavyweight, but we're debugging anyway.
> -     */
> -    tb_flush(cpu);
> -}
>   #endif



  reply	other threads:[~2023-11-28 11:09 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-20 19:54 [PATCH for-6.1 v6 00/17] tcg: breakpoint reorg Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 01/17] accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNS Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 02/17] accel/tcg: Move curr_cflags into cpu-exec.c Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 03/17] target/alpha: Drop goto_tb path in gen_call_pal Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 04/17] accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 05/17] accel/tcg: Drop CF_NO_GOTO_PTR from -d nochain Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 06/17] accel/tcg: Handle -singlestep in curr_cflags Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 07/17] accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomic Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 08/17] hw/core: Introduce TCGCPUOps.debug_check_breakpoint Richard Henderson
2021-07-21 10:33   ` Alex Bennée
2021-07-20 19:54 ` [PATCH for-6.1 v6 09/17] target/arm: Implement debug_check_breakpoint Richard Henderson
2021-07-21 10:35   ` Alex Bennée
2021-07-20 19:54 ` [PATCH for-6.1 v6 10/17] target/i386: " Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 11/17] hw/core: Introduce CPUClass.gdb_adjust_breakpoint Richard Henderson
2021-07-20 20:56   ` Peter Maydell
2021-07-20 21:08     ` Richard Henderson
2021-07-20 21:53       ` Philippe Mathieu-Daudé
2021-07-20 22:23         ` Philippe Mathieu-Daudé
2021-07-21  9:56           ` Alex Bennée
2021-07-21  6:12         ` Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 12/17] target/avr: Implement gdb_adjust_breakpoint Richard Henderson
2021-07-20 22:09   ` Philippe Mathieu-Daudé
2021-07-20 19:54 ` [PATCH for-6.1 v6 13/17] accel/tcg: Merge tb_find into its only caller Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 14/17] accel/tcg: Move breakpoint recognition outside translation Richard Henderson
2023-11-28 11:08   ` Philippe Mathieu-Daudé [this message]
2023-11-28 18:05     ` Richard Henderson
2023-11-29 15:41       ` Max Filippov
2021-07-20 19:54 ` [PATCH for-6.1 v6 15/17] accel/tcg: Remove TranslatorOps.breakpoint_check Richard Henderson
2021-07-20 20:45   ` Peter Maydell
2021-07-20 22:11   ` Philippe Mathieu-Daudé
2021-07-20 19:54 ` [PATCH for-6.1 v6 16/17] accel/tcg: Hoist tb_cflags to a local in translator_loop Richard Henderson
2021-07-20 19:54 ` [PATCH for-6.1 v6 17/17] accel/tcg: Record singlestep_enabled in tb->cflags Richard Henderson
2021-07-20 20:47   ` Peter Maydell
2021-07-21 10:38   ` Alex Bennée
2021-07-21 16:41     ` Richard Henderson
2021-07-21 16:48       ` Alex Bennée
2021-07-20 21:47 ` [PATCH for-6.1 v6 00/17] tcg: breakpoint reorg Mark Cave-Ayland

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