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[173.197.98.125]) by smtp.gmail.com with ESMTPSA id 6-20020a170902e9c600b001db70183611sm10248011plk.270.2024.02.22.11.42.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Feb 2024 11:42:18 -0800 (PST) Message-ID: <7a8e193b-c266-4723-9dae-198a975d77f7@linaro.org> Date: Thu, 22 Feb 2024 09:42:15 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 04/22] target/arm: Implement ALLINT MSR (immediate) Content-Language: en-US From: Richard Henderson To: Jinjie Ruan , peter.maydell@linaro.org, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20240221130823.677762-1-ruanjinjie@huawei.com> <20240221130823.677762-5-ruanjinjie@huawei.com> <9fb9c74e-e4d3-4a8b-b736-c8603414245c@linaro.org> <0911d6a4-7fd6-4d0f-83a8-ec4ba8420297@linaro.org> In-Reply-To: <0911d6a4-7fd6-4d0f-83a8-ec4ba8420297@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/21/24 10:41, Richard Henderson wrote: > Ho hum..  I just noticed that TALLINT only traps immediate write of 1, not also immediate > write of 0.  So one helper for both MSR Xt and MSR imm is not practical. Quick follow up to say that means you can do static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a) { if (!dc_isar_feature(aa64_nmi, s) || s->current_el == 0 || (a->imm & ~1)) { return false; } if (!a->imm) { clear_pstate_bits(PSTATE_ALLINT); } else if (arm_dc_feature(s, ARM_FEATURE_EL2) && s->current_el == 1) { /* Use helper for runtime check against HCRX_EL2.TALLINT. */ gen_helper_msr_set_allint_el1(tcg_env); } else { set_pstate_bits(PSTATE_ALLINT); } return true; } Generate inline bit ops whenever TALLINT does not apply. This also means the helper need not check current_el, because we've already done it here. r~