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References: <20180620120620.12806-1-yongbok.kim@mips.com>
	<20180620120620.12806-12-yongbok.kim@mips.com>
From: Richard Henderson <richard.henderson@linaro.org>
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Date: Sun, 24 Jun 2018 16:59:49 -0700
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Subject: Re: [Qemu-devel] [PATCH 11/35] target/mips: Add nanoMIPS pool32a0
 instructions
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To: Yongbok Kim <yongbok.kim@mips.com>, qemu-devel@nongnu.org
Cc: Aleksandar.Markovic@mips.com, Paul.Burton@mips.com, Stefan.Markovic@mips.com, Matthew.Fortune@mips.com, James.Hogan@mips.com, aurelien@aurel32.net

On 06/20/2018 05:05 AM, Yongbok Kim wrote:
> +    case NM_SOV:
> +    {
> +        TCGv t0 = tcg_temp_local_new();
> +        TCGv t1 = tcg_temp_new();
> +        TCGv t2 = tcg_temp_new();
> +        TCGLabel *l1 = gen_new_label();
> +
> +        gen_load_gpr(t1, rs);
> +        gen_load_gpr(t2, rt);
> +        tcg_gen_add_tl(t0, t1, t2);
> +        tcg_gen_ext32s_tl(t0, t0);
> +        tcg_gen_xor_tl(t1, t1, t2);
> +        tcg_gen_xor_tl(t2, t0, t2);
> +        tcg_gen_andc_tl(t1, t2, t1);
> +
> +        tcg_gen_movi_tl(t0, 0);
> +        tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
> +        /* operands of same sign, result different sign */
> +
> +        tcg_gen_movi_tl(t0, 1);
> +        gen_set_label(l1);
> +        gen_store_gpr(t0, rd);

No need for branch.  This is just extracting the sign bit, so

  tcg_gen_shri_tl(t0, t1, TARGET_LONG_BITS - 1);


r~