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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Hervé Poussineau" <hpoussin@reactos.org>,
	"Aleksandar Rikalo" <arikalo@gmail.com>,
	"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
	"Bernhard Beschow" <shentey@gmail.com>,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: Re: [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState
Date: Tue, 21 Jan 2025 17:20:49 +0100	[thread overview]
Message-ID: <7ad57755-90e7-41cf-a9b4-48827e096f60@linaro.org> (raw)
In-Reply-To: <20250121161817.33654-7-philmd@linaro.org>

On 21/1/25 17:18, Philippe Mathieu-Daudé wrote:
> There are always 8 IRQs created with a MIPS CPU.
> Allocate their state once in CPUMIPSState, initialize
> them in place in cpu_mips_irq_init_cpu(). Update hw/ uses.
> 
> Move cpu_mips_irq_init_cpu() declaration from "cpu.h"
> to "internal.h", as it shouldn't be accessible from hw/.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/mips/cpu.h               |  4 ++--
>   target/mips/internal.h          |  2 ++
>   hw/intc/mips_gic.c              |  4 ++--
>   hw/mips/fuloong2e.c             |  4 ++--
>   hw/mips/jazz.c                  |  6 +++---
>   hw/mips/loongson3_virt.c        |  4 ++--
>   hw/mips/malta.c                 |  4 ++--
>   hw/mips/mipssim.c               |  4 ++--
>   target/mips/system/cp0_timer.c  |  4 ++--
>   target/mips/system/interrupts.c | 11 +++--------
>   10 files changed, 22 insertions(+), 25 deletions(-)
> 
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index e5767ea9cf3..25a19b61913 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -8,6 +8,7 @@
>   #endif
>   #include "fpu/softfloat-types.h"
>   #include "hw/clock.h"
> +#include "hw/irq.h"
>   #include "mips-defs.h"
>   
>   typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
> @@ -1177,7 +1178,7 @@ typedef struct CPUArchState {
>       CPUMIPSMVPContext *mvp;
>   #if !defined(CONFIG_USER_ONLY)
>       CPUMIPSTLBContext *tlb;
> -    qemu_irq irq[8];
> +    IRQState irq[8];
>       MemoryRegion *itc_tag; /* ITC Configuration Tags */


> diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
> index 9a638f596bd..ccebc56adec 100644
> --- a/hw/mips/fuloong2e.c
> +++ b/hw/mips/fuloong2e.c
> @@ -278,7 +278,7 @@ static void mips_fuloong2e_init(MachineState *machine)
>       }
>   
>       /* North bridge, Bonito --> IP2 */
> -    pci_bus = bonito_init(env->irq[2]);
> +    pci_bus = bonito_init(&env->irq[2]);

Orthogonal, but thinking of heterogeneous emulation, at some point
we'll need to expose vCPU IRQs as QDev GPIO.



  reply	other threads:[~2025-01-21 16:21 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-21 16:18 [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 1/6] hw/pci-host/bonito: Expose output IRQ as QDev GPIO Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 2/6] target/mips: Create clock *after* accelerator vCPU is realized Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize Philippe Mathieu-Daudé
2025-01-21 23:07   ` Richard Henderson
2025-01-21 16:18 ` [PATCH 4/6] target/mips: Pass env to cpu_mips_clock_init() Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 5/6] target/mips: Move CPU timer from hw/mips/ to target/mips/system/ Philippe Mathieu-Daudé
2025-01-21 23:08   ` Richard Henderson
2025-01-21 16:18 ` [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState Philippe Mathieu-Daudé
2025-01-21 16:20   ` Philippe Mathieu-Daudé [this message]
2025-01-21 23:12   ` Richard Henderson
2025-01-21 16:42 ` [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé

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