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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38bf3214d62sm13587734f8f.1.2025.01.21.08.20.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jan 2025 08:20:50 -0800 (PST) Message-ID: <7ad57755-90e7-41cf-a9b4-48827e096f60@linaro.org> Date: Tue, 21 Jan 2025 17:20:49 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState To: qemu-devel@nongnu.org Cc: =?UTF-8?Q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , Bernhard Beschow , Huacai Chen , Aurelien Jarno References: <20250121161817.33654-1-philmd@linaro.org> <20250121161817.33654-7-philmd@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250121161817.33654-7-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 21/1/25 17:18, Philippe Mathieu-Daudé wrote: > There are always 8 IRQs created with a MIPS CPU. > Allocate their state once in CPUMIPSState, initialize > them in place in cpu_mips_irq_init_cpu(). Update hw/ uses. > > Move cpu_mips_irq_init_cpu() declaration from "cpu.h" > to "internal.h", as it shouldn't be accessible from hw/. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/cpu.h | 4 ++-- > target/mips/internal.h | 2 ++ > hw/intc/mips_gic.c | 4 ++-- > hw/mips/fuloong2e.c | 4 ++-- > hw/mips/jazz.c | 6 +++--- > hw/mips/loongson3_virt.c | 4 ++-- > hw/mips/malta.c | 4 ++-- > hw/mips/mipssim.c | 4 ++-- > target/mips/system/cp0_timer.c | 4 ++-- > target/mips/system/interrupts.c | 11 +++-------- > 10 files changed, 22 insertions(+), 25 deletions(-) > > diff --git a/target/mips/cpu.h b/target/mips/cpu.h > index e5767ea9cf3..25a19b61913 100644 > --- a/target/mips/cpu.h > +++ b/target/mips/cpu.h > @@ -8,6 +8,7 @@ > #endif > #include "fpu/softfloat-types.h" > #include "hw/clock.h" > +#include "hw/irq.h" > #include "mips-defs.h" > > typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; > @@ -1177,7 +1178,7 @@ typedef struct CPUArchState { > CPUMIPSMVPContext *mvp; > #if !defined(CONFIG_USER_ONLY) > CPUMIPSTLBContext *tlb; > - qemu_irq irq[8]; > + IRQState irq[8]; > MemoryRegion *itc_tag; /* ITC Configuration Tags */ > diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c > index 9a638f596bd..ccebc56adec 100644 > --- a/hw/mips/fuloong2e.c > +++ b/hw/mips/fuloong2e.c > @@ -278,7 +278,7 @@ static void mips_fuloong2e_init(MachineState *machine) > } > > /* North bridge, Bonito --> IP2 */ > - pci_bus = bonito_init(env->irq[2]); > + pci_bus = bonito_init(&env->irq[2]); Orthogonal, but thinking of heterogeneous emulation, at some point we'll need to expose vCPU IRQs as QDev GPIO.