* [PATCH 1/6] hw/pci-host/bonito: Expose output IRQ as QDev GPIO
2025-01-21 16:18 [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
@ 2025-01-21 16:18 ` Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 2/6] target/mips: Create clock *after* accelerator vCPU is realized Philippe Mathieu-Daudé
` (5 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-21 16:18 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Aleksandar Rikalo, Jiaxun Yang,
Bernhard Beschow, Philippe Mathieu-Daudé, Huacai Chen,
Aurelien Jarno
Expose IRQ using qdev_init_gpio_out() in bonito_host_realize(),
wire it using qdev_connect_gpio_out() in bonito_init().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/mips/mips.h | 2 +-
hw/mips/fuloong2e.c | 2 +-
hw/pci-host/bonito.c | 14 +++++++-------
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h
index 101799f7d3e..1176291cca6 100644
--- a/include/hw/mips/mips.h
+++ b/include/hw/mips/mips.h
@@ -10,7 +10,7 @@
#include "exec/memory.h"
/* bonito.c */
-PCIBus *bonito_init(qemu_irq *pic);
+PCIBus *bonito_init(qemu_irq irq);
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 16b6a5129e7..160ceb769dc 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -282,7 +282,7 @@ static void mips_fuloong2e_init(MachineState *machine)
cpu_mips_clock_init(cpu);
/* North bridge, Bonito --> IP2 */
- pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));
+ pci_bus = bonito_init(env->irq[2]);
/* South bridge -> IP5 */
pci_dev = pci_new_multifunction(PCI_DEVFN(FULOONG2E_VIA_SLOT, 0),
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
index 49669148923..6bc66c9e227 100644
--- a/hw/pci-host/bonito.c
+++ b/hw/pci-host/bonito.c
@@ -234,7 +234,7 @@ typedef struct PCIBonitoState PCIBonitoState;
struct BonitoState {
PCIHostState parent_obj;
- qemu_irq *pic;
+ qemu_irq irq;
PCIBonitoState *pci_dev;
MemoryRegion pci_mem;
};
@@ -554,17 +554,16 @@ static const MemoryRegionOps bonito_spciconf_ops = {
static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
{
BonitoState *s = opaque;
- qemu_irq *pic = s->pic;
PCIBonitoState *bonito_state = s->pci_dev;
int internal_irq = irq_num - BONITO_IRQ_BASE;
if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
- qemu_irq_pulse(*pic);
+ qemu_irq_pulse(s->irq);
} else { /* level triggered */
if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
- qemu_irq_raise(*pic);
+ qemu_irq_raise(s->irq);
} else {
- qemu_irq_lower(*pic);
+ qemu_irq_lower(s->irq);
}
}
}
@@ -631,6 +630,7 @@ static void bonito_host_realize(DeviceState *dev, Error **errp)
BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
+ qdev_init_gpio_out(dev, &bs->irq, 1);
memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
phb->bus = pci_register_root_bus(dev, "pci",
pci_bonito_set_irq, pci_bonito_map_irq,
@@ -734,7 +734,7 @@ static void bonito_pci_realize(PCIDevice *dev, Error **errp)
pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
}
-PCIBus *bonito_init(qemu_irq *pic)
+PCIBus *bonito_init(qemu_irq irq)
{
DeviceState *dev;
BonitoState *pcihost;
@@ -745,8 +745,8 @@ PCIBus *bonito_init(qemu_irq *pic)
dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE);
phb = PCI_HOST_BRIDGE(dev);
pcihost = BONITO_PCI_HOST_BRIDGE(dev);
- pcihost->pic = pic;
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+ qdev_connect_gpio_out(dev, 0, irq);
d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
s = PCI_BONITO(d);
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/6] target/mips: Create clock *after* accelerator vCPU is realized
2025-01-21 16:18 [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 1/6] hw/pci-host/bonito: Expose output IRQ as QDev GPIO Philippe Mathieu-Daudé
@ 2025-01-21 16:18 ` Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize Philippe Mathieu-Daudé
` (4 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-21 16:18 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Aleksandar Rikalo, Jiaxun Yang,
Bernhard Beschow, Philippe Mathieu-Daudé, Huacai Chen,
Aurelien Jarno, Richard Henderson
Architecture specific hardware doesn't have a particular dependency
on the accelerator vCPU (created with cpu_exec_realizefn), and can
be initialized *after* the vCPU is realized.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 0b3ac4e60a3..028a3c91afb 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -462,20 +462,6 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
Error *local_err = NULL;
- if (!clock_get(cpu->clock)) {
-#ifndef CONFIG_USER_ONLY
- if (!qtest_enabled()) {
- g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT);
-
- warn_report("CPU input clock is not connected to any output clock, "
- "using default frequency of %s.", cpu_freq_str);
- }
-#endif
- /* Initialize the frequency in case the clock remains unconnected. */
- clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
- }
- mips_cp0_period_set(cpu);
-
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -490,6 +476,20 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
fpu_init(env, env->cpu_model);
mvp_init(env);
+ if (!clock_get(cpu->clock)) {
+#ifndef CONFIG_USER_ONLY
+ if (!qtest_enabled()) {
+ g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT);
+
+ warn_report("CPU input clock is not connected to any output clock, "
+ "using default frequency of %s.", cpu_freq_str);
+ }
+#endif
+ /* Initialize the frequency in case the clock remains unconnected. */
+ clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
+ }
+ mips_cp0_period_set(cpu);
+
cpu_reset(cs);
qemu_init_vcpu(cs);
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize
2025-01-21 16:18 [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 1/6] hw/pci-host/bonito: Expose output IRQ as QDev GPIO Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 2/6] target/mips: Create clock *after* accelerator vCPU is realized Philippe Mathieu-Daudé
@ 2025-01-21 16:18 ` Philippe Mathieu-Daudé
2025-01-21 23:07 ` Richard Henderson
2025-01-21 16:18 ` [PATCH 4/6] target/mips: Pass env to cpu_mips_clock_init() Philippe Mathieu-Daudé
` (3 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-21 16:18 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Aleksandar Rikalo, Jiaxun Yang,
Bernhard Beschow, Philippe Mathieu-Daudé, Huacai Chen,
Aurelien Jarno
The MIPS timer and IRQs are tied to the CPU. Creating them outside
in board code isn't correct. Do it once in the DeviceRealize() handler.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/cps.c | 4 ----
hw/mips/fuloong2e.c | 4 ----
hw/mips/jazz.c | 4 ----
hw/mips/loongson3_virt.c | 4 ----
hw/mips/malta.c | 4 ----
hw/mips/mipssim.c | 4 ----
target/mips/cpu.c | 5 +++++
7 files changed, 5 insertions(+), 24 deletions(-)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 0d8cbdc8924..f85fb4458af 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -91,10 +91,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
return;
}
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
if (cpu_mips_itu_supported(env)) {
itu_present = true;
/* Attach ITC Tag to the VP */
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 160ceb769dc..9a638f596bd 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -277,10 +277,6 @@ static void mips_fuloong2e_init(MachineState *machine)
}
}
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
/* North bridge, Bonito --> IP2 */
pci_bus = bonito_init(env->irq[2]);
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index c89610639a9..ce4a702aa53 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -259,10 +259,6 @@ static void mips_jazz_init(MachineState *machine,
exit(1);
}
- /* Init CPU internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
/* Chipset */
rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
sysbus = SYS_BUS_DEVICE(rc4030);
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index f3cc7a8376f..91070824bbe 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -568,10 +568,6 @@ static void mips_loongson3_virt_init(MachineState *machine)
/* init CPUs */
cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
-
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
qemu_register_reset(main_cpu_reset, cpu);
if (!kvm_enabled()) {
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 4e9cccaa347..ac3b16229c8 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1037,10 +1037,6 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
for (i = 0; i < ms->smp.cpus; i++) {
cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk,
TARGET_BIG_ENDIAN);
-
- /* Init internal devices */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
qemu_register_reset(main_cpu_reset, cpu);
}
diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c
index a294779a82b..d4b3b043053 100644
--- a/hw/mips/mipssim.c
+++ b/hw/mips/mipssim.c
@@ -203,10 +203,6 @@ mips_mipssim_init(MachineState *machine)
reset_info->vector = load_kernel();
}
- /* Init CPU internal devices. */
- cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
-
/*
* Register 64 KB of ISA IO space at 0x1fd00000. But without interrupts
* (except for the hardcoded serial port interrupt) -device cannot work,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 028a3c91afb..95df8985bc6 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -476,6 +476,11 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
fpu_init(env, env->cpu_model);
mvp_init(env);
+ /* Init internal devices */
+#ifndef CONFIG_USER_ONLY
+ cpu_mips_irq_init_cpu(cpu);
+ cpu_mips_clock_init(cpu);
+#endif
if (!clock_get(cpu->clock)) {
#ifndef CONFIG_USER_ONLY
if (!qtest_enabled()) {
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize
2025-01-21 16:18 ` [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize Philippe Mathieu-Daudé
@ 2025-01-21 23:07 ` Richard Henderson
0 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2025-01-21 23:07 UTC (permalink / raw)
To: qemu-devel
On 1/21/25 08:18, Philippe Mathieu-Daudé wrote:
> The MIPS timer and IRQs are tied to the CPU. Creating them outside
> in board code isn't correct. Do it once in the DeviceRealize() handler.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> hw/mips/cps.c | 4 ----
> hw/mips/fuloong2e.c | 4 ----
> hw/mips/jazz.c | 4 ----
> hw/mips/loongson3_virt.c | 4 ----
> hw/mips/malta.c | 4 ----
> hw/mips/mipssim.c | 4 ----
> target/mips/cpu.c | 5 +++++
> 7 files changed, 5 insertions(+), 24 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/6] target/mips: Pass env to cpu_mips_clock_init()
2025-01-21 16:18 [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-01-21 16:18 ` [PATCH 3/6] target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize Philippe Mathieu-Daudé
@ 2025-01-21 16:18 ` Philippe Mathieu-Daudé
2025-01-21 16:18 ` [PATCH 5/6] target/mips: Move CPU timer from hw/mips/ to target/mips/system/ Philippe Mathieu-Daudé
` (2 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-21 16:18 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Aleksandar Rikalo, Jiaxun Yang,
Bernhard Beschow, Philippe Mathieu-Daudé, Huacai Chen,
Aurelien Jarno
Simplify cpu_mips_clock_init() by having it directly take
a CPU env, move its declaration from "cpu.h" to "internal.h",
as it shouldn't be accessible from hw/.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu.h | 1 -
target/mips/internal.h | 1 +
target/mips/cpu.c | 2 +-
target/mips/system/cp0_timer.c | 4 +---
4 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index f6877ece8b4..e5767ea9cf3 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1361,7 +1361,6 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
/* HW declaration specific to the MIPS target */
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
-void cpu_mips_clock_init(MIPSCPU *cpu);
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 28eb28936ba..69452aae5bc 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -214,6 +214,7 @@ void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
void cpu_mips_start_count(CPUMIPSState *env);
void cpu_mips_stop_count(CPUMIPSState *env);
+void cpu_mips_clock_init(CPUMIPSState *env);
static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
{
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 95df8985bc6..99f442a4b98 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -479,7 +479,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
/* Init internal devices */
#ifndef CONFIG_USER_ONLY
cpu_mips_irq_init_cpu(cpu);
- cpu_mips_clock_init(cpu);
+ cpu_mips_clock_init(env);
#endif
if (!clock_get(cpu->clock)) {
#ifndef CONFIG_USER_ONLY
diff --git a/target/mips/system/cp0_timer.c b/target/mips/system/cp0_timer.c
index ca16945cee1..07641cab521 100644
--- a/target/mips/system/cp0_timer.c
+++ b/target/mips/system/cp0_timer.c
@@ -133,10 +133,8 @@ static void mips_timer_cb(void *opaque)
cpu_mips_timer_expire(env);
}
-void cpu_mips_clock_init(MIPSCPU *cpu)
+void cpu_mips_clock_init(CPUMIPSState *env)
{
- CPUMIPSState *env = &cpu->env;
-
/*
* If we're in KVM mode, don't create the periodic timer, that is handled in
* kernel.
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 5/6] target/mips: Move CPU timer from hw/mips/ to target/mips/system/
2025-01-21 16:18 [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2025-01-21 16:18 ` [PATCH 4/6] target/mips: Pass env to cpu_mips_clock_init() Philippe Mathieu-Daudé
@ 2025-01-21 16:18 ` Philippe Mathieu-Daudé
2025-01-21 23:08 ` Richard Henderson
2025-01-21 16:18 ` [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState Philippe Mathieu-Daudé
2025-01-21 16:42 ` [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
6 siblings, 1 reply; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-21 16:18 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Aleksandar Rikalo, Jiaxun Yang,
Bernhard Beschow, Philippe Mathieu-Daudé, Huacai Chen,
Aurelien Jarno
MIPS CPU timer is tied to the CPU, no point of modelling it as
a general timer device. Move mips_int.c to target/mips/system/.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/mips_int.c => target/mips/system/interrupts.c | 0
hw/mips/meson.build | 2 +-
target/mips/system/meson.build | 1 +
3 files changed, 2 insertions(+), 1 deletion(-)
rename hw/mips/mips_int.c => target/mips/system/interrupts.c (100%)
diff --git a/hw/mips/mips_int.c b/target/mips/system/interrupts.c
similarity index 100%
rename from hw/mips/mips_int.c
rename to target/mips/system/interrupts.c
diff --git a/hw/mips/meson.build b/hw/mips/meson.build
index fcbee53bb32..6dd97331ca7 100644
--- a/hw/mips/meson.build
+++ b/hw/mips/meson.build
@@ -1,5 +1,5 @@
mips_ss = ss.source_set()
-mips_ss.add(files('bootloader.c', 'mips_int.c'))
+mips_ss.add(files('bootloader.c'))
common_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c'))
mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c'))
mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c'))
diff --git a/target/mips/system/meson.build b/target/mips/system/meson.build
index 498cf289d6f..cf232c9edad 100644
--- a/target/mips/system/meson.build
+++ b/target/mips/system/meson.build
@@ -2,6 +2,7 @@ mips_system_ss.add(files(
'addr.c',
'cp0.c',
'cp0_timer.c',
+ 'interrupts.c',
'machine.c',
'mips-qmp-cmds.c',
'physaddr.c',
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 5/6] target/mips: Move CPU timer from hw/mips/ to target/mips/system/
2025-01-21 16:18 ` [PATCH 5/6] target/mips: Move CPU timer from hw/mips/ to target/mips/system/ Philippe Mathieu-Daudé
@ 2025-01-21 23:08 ` Richard Henderson
0 siblings, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2025-01-21 23:08 UTC (permalink / raw)
To: qemu-devel
On 1/21/25 08:18, Philippe Mathieu-Daudé wrote:
> MIPS CPU timer is tied to the CPU, no point of modelling it as
> a general timer device. Move mips_int.c to target/mips/system/.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/mips/mips_int.c => target/mips/system/interrupts.c | 0
> hw/mips/meson.build | 2 +-
> target/mips/system/meson.build | 1 +
> 3 files changed, 2 insertions(+), 1 deletion(-)
> rename hw/mips/mips_int.c => target/mips/system/interrupts.c (100%)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
>
> diff --git a/hw/mips/mips_int.c b/target/mips/system/interrupts.c
> similarity index 100%
> rename from hw/mips/mips_int.c
> rename to target/mips/system/interrupts.c
> diff --git a/hw/mips/meson.build b/hw/mips/meson.build
> index fcbee53bb32..6dd97331ca7 100644
> --- a/hw/mips/meson.build
> +++ b/hw/mips/meson.build
> @@ -1,5 +1,5 @@
> mips_ss = ss.source_set()
> -mips_ss.add(files('bootloader.c', 'mips_int.c'))
> +mips_ss.add(files('bootloader.c'))
> common_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c'))
> mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c'))
> mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c'))
> diff --git a/target/mips/system/meson.build b/target/mips/system/meson.build
> index 498cf289d6f..cf232c9edad 100644
> --- a/target/mips/system/meson.build
> +++ b/target/mips/system/meson.build
> @@ -2,6 +2,7 @@ mips_system_ss.add(files(
> 'addr.c',
> 'cp0.c',
> 'cp0_timer.c',
> + 'interrupts.c',
> 'machine.c',
> 'mips-qmp-cmds.c',
> 'physaddr.c',
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState
2025-01-21 16:18 [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2025-01-21 16:18 ` [PATCH 5/6] target/mips: Move CPU timer from hw/mips/ to target/mips/system/ Philippe Mathieu-Daudé
@ 2025-01-21 16:18 ` Philippe Mathieu-Daudé
2025-01-21 16:20 ` Philippe Mathieu-Daudé
2025-01-21 23:12 ` Richard Henderson
2025-01-21 16:42 ` [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
6 siblings, 2 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-21 16:18 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Aleksandar Rikalo, Jiaxun Yang,
Bernhard Beschow, Philippe Mathieu-Daudé, Huacai Chen,
Aurelien Jarno
There are always 8 IRQs created with a MIPS CPU.
Allocate their state once in CPUMIPSState, initialize
them in place in cpu_mips_irq_init_cpu(). Update hw/ uses.
Move cpu_mips_irq_init_cpu() declaration from "cpu.h"
to "internal.h", as it shouldn't be accessible from hw/.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu.h | 4 ++--
target/mips/internal.h | 2 ++
hw/intc/mips_gic.c | 4 ++--
hw/mips/fuloong2e.c | 4 ++--
hw/mips/jazz.c | 6 +++---
hw/mips/loongson3_virt.c | 4 ++--
hw/mips/malta.c | 4 ++--
hw/mips/mipssim.c | 4 ++--
target/mips/system/cp0_timer.c | 4 ++--
target/mips/system/interrupts.c | 11 +++--------
10 files changed, 22 insertions(+), 25 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index e5767ea9cf3..25a19b61913 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -8,6 +8,7 @@
#endif
#include "fpu/softfloat-types.h"
#include "hw/clock.h"
+#include "hw/irq.h"
#include "mips-defs.h"
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
@@ -1177,7 +1178,7 @@ typedef struct CPUArchState {
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
- qemu_irq irq[8];
+ IRQState irq[8];
MemoryRegion *itc_tag; /* ITC Configuration Tags */
/* Loongson IOCSR memory */
@@ -1360,7 +1361,6 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
/* HW declaration specific to the MIPS target */
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
-void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 69452aae5bc..63a56254bee 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -160,6 +160,8 @@ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
+void cpu_mips_irq_init_cpu(MIPSCPU *cpu);
+
extern const VMStateDescription vmstate_mips_cpu;
static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c
index 5e3cbeabece..e5b16538305 100644
--- a/hw/intc/mips_gic.c
+++ b/hw/intc/mips_gic.c
@@ -50,7 +50,7 @@ static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin)
pin + GIC_CPU_PIN_OFFSET,
ored_level);
} else {
- qemu_set_irq(gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET],
+ qemu_set_irq(&gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET],
ored_level);
}
}
@@ -203,7 +203,7 @@ static void gic_timer_expire_cb(void *opaque, uint32_t vp_index)
if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) {
/* it is safe to set the irq high regardless of other GIC IRQs */
uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK);
- qemu_irq_raise(gic->vps[vp_index].env->irq
+ qemu_irq_raise(&gic->vps[vp_index].env->irq
[pin + GIC_CPU_PIN_OFFSET]);
}
}
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 9a638f596bd..ccebc56adec 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -278,7 +278,7 @@ static void mips_fuloong2e_init(MachineState *machine)
}
/* North bridge, Bonito --> IP2 */
- pci_bus = bonito_init(env->irq[2]);
+ pci_bus = bonito_init(&env->irq[2]);
/* South bridge -> IP5 */
pci_dev = pci_new_multifunction(PCI_DEVFN(FULOONG2E_VIA_SLOT, 0),
@@ -296,7 +296,7 @@ static void mips_fuloong2e_init(MachineState *machine)
object_resolve_path_component(OBJECT(pci_dev),
"rtc"),
"date");
- qdev_connect_gpio_out_named(DEVICE(pci_dev), "intr", 0, env->irq[5]);
+ qdev_connect_gpio_out_named(DEVICE(pci_dev), "intr", 0, &env->irq[5]);
dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide"));
pci_ide_create_devs(PCI_DEVICE(dev));
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index ce4a702aa53..85728ab45ad 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -262,8 +262,8 @@ static void mips_jazz_init(MachineState *machine,
/* Chipset */
rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
sysbus = SYS_BUS_DEVICE(rc4030);
- sysbus_connect_irq(sysbus, 0, env->irq[6]);
- sysbus_connect_irq(sysbus, 1, env->irq[3]);
+ sysbus_connect_irq(sysbus, 0, &env->irq[6]);
+ sysbus_connect_irq(sysbus, 1, &env->irq[3]);
memory_region_add_subregion(address_space, 0x80000000,
sysbus_mmio_get_region(sysbus, 0));
memory_region_add_subregion(address_space, 0xf0000000,
@@ -284,7 +284,7 @@ static void mips_jazz_init(MachineState *machine,
isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
/* ISA devices */
- i8259 = i8259_init(isa_bus, env->irq[4]);
+ i8259 = i8259_init(isa_bus, &env->irq[4]);
isa_bus_register_input_irqs(isa_bus, i8259);
i8257_dma_init(OBJECT(rc4030), isa_bus, 0);
pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index 91070824bbe..f1403826fc5 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -573,7 +573,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
if (!kvm_enabled()) {
hwaddr base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base;
base += core * 0x100;
- qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]);
+ qdev_connect_gpio_out(ipi, i, &cpu->env.irq[6]);
sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, base);
}
@@ -594,7 +594,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
for (ip = 0; ip < 4 ; ip++) {
int pin = core * LOONGSON3_CORE_PER_NODE + ip;
sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
- pin, cpu->env.irq[ip + 2]);
+ pin, &cpu->env.irq[ip + 2]);
}
}
env = &MIPS_CPU(first_cpu)->env;
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index ac3b16229c8..425d836f476 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1042,8 +1042,8 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
cpu = MIPS_CPU(first_cpu);
env = &cpu->env;
- *i8259_irq = env->irq[2];
- *cbus_irq = env->irq[4];
+ *i8259_irq = &env->irq[2];
+ *cbus_irq = &env->irq[4];
}
static void create_cps(MachineState *ms, MaltaState *s,
diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c
index d4b3b043053..4277b40d723 100644
--- a/hw/mips/mipssim.c
+++ b/hw/mips/mipssim.c
@@ -223,13 +223,13 @@ mips_mipssim_init(MachineState *machine)
qdev_prop_set_uint8(dev, "regshift", 0);
qdev_prop_set_uint8(dev, "endianness", DEVICE_LITTLE_ENDIAN);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, env->irq[4]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, &env->irq[4]);
memory_region_add_subregion(get_system_io(), 0x3f8,
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
}
/* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
- mipsnet_init(0x4200, env->irq[2]);
+ mipsnet_init(0x4200, &env->irq[2]);
}
static void mips_mipssim_machine_init(MachineClass *mc)
diff --git a/target/mips/system/cp0_timer.c b/target/mips/system/cp0_timer.c
index 07641cab521..5600af66bc4 100644
--- a/target/mips/system/cp0_timer.c
+++ b/target/mips/system/cp0_timer.c
@@ -57,7 +57,7 @@ static void cpu_mips_timer_expire(CPUMIPSState *env)
if (env->insn_flags & ISA_MIPS_R2) {
env->CP0_Cause |= 1 << CP0Ca_TI;
}
- qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+ qemu_irq_raise(&env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
uint32_t cpu_mips_get_count(CPUMIPSState *env)
@@ -105,7 +105,7 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value)
if (env->insn_flags & ISA_MIPS_R2) {
env->CP0_Cause &= ~(1 << CP0Ca_TI);
}
- qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
+ qemu_irq_lower(&env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
void cpu_mips_start_count(CPUMIPSState *env)
diff --git a/target/mips/system/interrupts.c b/target/mips/system/interrupts.c
index 26fdb934f50..f85bb66de3c 100644
--- a/target/mips/system/interrupts.c
+++ b/target/mips/system/interrupts.c
@@ -25,6 +25,7 @@
#include "hw/irq.h"
#include "system/kvm.h"
#include "kvm_mips.h"
+#include "internal.h"
static void cpu_mips_irq_request(void *opaque, int irq, int level)
{
@@ -58,14 +59,8 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
void cpu_mips_irq_init_cpu(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;
- qemu_irq *qi;
- int i;
- qi = qemu_allocate_irqs(cpu_mips_irq_request, cpu, 8);
- for (i = 0; i < 8; i++) {
- env->irq[i] = qi[i];
- }
- g_free(qi);
+ qemu_init_irqs(env->irq, ARRAY_SIZE(env->irq), cpu_mips_irq_request, cpu);
}
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
@@ -74,5 +69,5 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
return;
}
- qemu_set_irq(env->irq[irq], level);
+ qemu_set_irq(&env->irq[irq], level);
}
--
2.47.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState
2025-01-21 16:18 ` [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState Philippe Mathieu-Daudé
@ 2025-01-21 16:20 ` Philippe Mathieu-Daudé
2025-01-21 23:12 ` Richard Henderson
1 sibling, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-21 16:20 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Aleksandar Rikalo, Jiaxun Yang,
Bernhard Beschow, Huacai Chen, Aurelien Jarno
On 21/1/25 17:18, Philippe Mathieu-Daudé wrote:
> There are always 8 IRQs created with a MIPS CPU.
> Allocate their state once in CPUMIPSState, initialize
> them in place in cpu_mips_irq_init_cpu(). Update hw/ uses.
>
> Move cpu_mips_irq_init_cpu() declaration from "cpu.h"
> to "internal.h", as it shouldn't be accessible from hw/.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/cpu.h | 4 ++--
> target/mips/internal.h | 2 ++
> hw/intc/mips_gic.c | 4 ++--
> hw/mips/fuloong2e.c | 4 ++--
> hw/mips/jazz.c | 6 +++---
> hw/mips/loongson3_virt.c | 4 ++--
> hw/mips/malta.c | 4 ++--
> hw/mips/mipssim.c | 4 ++--
> target/mips/system/cp0_timer.c | 4 ++--
> target/mips/system/interrupts.c | 11 +++--------
> 10 files changed, 22 insertions(+), 25 deletions(-)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index e5767ea9cf3..25a19b61913 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -8,6 +8,7 @@
> #endif
> #include "fpu/softfloat-types.h"
> #include "hw/clock.h"
> +#include "hw/irq.h"
> #include "mips-defs.h"
>
> typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
> @@ -1177,7 +1178,7 @@ typedef struct CPUArchState {
> CPUMIPSMVPContext *mvp;
> #if !defined(CONFIG_USER_ONLY)
> CPUMIPSTLBContext *tlb;
> - qemu_irq irq[8];
> + IRQState irq[8];
> MemoryRegion *itc_tag; /* ITC Configuration Tags */
> diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
> index 9a638f596bd..ccebc56adec 100644
> --- a/hw/mips/fuloong2e.c
> +++ b/hw/mips/fuloong2e.c
> @@ -278,7 +278,7 @@ static void mips_fuloong2e_init(MachineState *machine)
> }
>
> /* North bridge, Bonito --> IP2 */
> - pci_bus = bonito_init(env->irq[2]);
> + pci_bus = bonito_init(&env->irq[2]);
Orthogonal, but thinking of heterogeneous emulation, at some point
we'll need to expose vCPU IRQs as QDev GPIO.
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState
2025-01-21 16:18 ` [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState Philippe Mathieu-Daudé
2025-01-21 16:20 ` Philippe Mathieu-Daudé
@ 2025-01-21 23:12 ` Richard Henderson
1 sibling, 0 replies; 12+ messages in thread
From: Richard Henderson @ 2025-01-21 23:12 UTC (permalink / raw)
To: qemu-devel
On 1/21/25 08:18, Philippe Mathieu-Daudé wrote:
> There are always 8 IRQs created with a MIPS CPU.
> Allocate their state once in CPUMIPSState, initialize
> them in place in cpu_mips_irq_init_cpu(). Update hw/ uses.
>
> Move cpu_mips_irq_init_cpu() declaration from "cpu.h"
> to "internal.h", as it shouldn't be accessible from hw/.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> target/mips/cpu.h | 4 ++--
> target/mips/internal.h | 2 ++
> hw/intc/mips_gic.c | 4 ++--
> hw/mips/fuloong2e.c | 4 ++--
> hw/mips/jazz.c | 6 +++---
> hw/mips/loongson3_virt.c | 4 ++--
> hw/mips/malta.c | 4 ++--
> hw/mips/mipssim.c | 4 ++--
> target/mips/system/cp0_timer.c | 4 ++--
> target/mips/system/interrupts.c | 11 +++--------
> 10 files changed, 22 insertions(+), 25 deletions(-)
Why move into CPUMIPSState and not MIPSCPU?
Is it because that's where irq[8] is currently?
I guess it doesn't matter much either way.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq()
2025-01-21 16:18 [PATCH 0/6] target/mips: Convert legacy qemu_allocate_irqs() to qemu_init_irq() Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2025-01-21 16:18 ` [PATCH 6/6] target/mips: Allocate CPU IRQs within CPUMIPSState Philippe Mathieu-Daudé
@ 2025-01-21 16:42 ` Philippe Mathieu-Daudé
6 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-01-21 16:42 UTC (permalink / raw)
To: qemu-devel
Cc: Hervé Poussineau, Aleksandar Rikalo, Jiaxun Yang,
Bernhard Beschow, Huacai Chen, Aurelien Jarno
On 21/1/25 17:18, Philippe Mathieu-Daudé wrote:
> IRQ cleanup in bonito64 in order to remove legacy qemu_allocate_irqs
> call in target/mips/.
>
> Philippe Mathieu-Daudé (6):
> hw/pci-host/bonito: Expose output IRQ as QDev GPIO
> target/mips: Create clock *after* accelerator vCPU is realized
> target/mips: Initialize CPU-specific timer/IRQs once in DeviceRealize
> target/mips: Pass env to cpu_mips_clock_init()
> target/mips: Move CPU timer from hw/mips/ to target/mips/system/
> target/mips: Allocate CPU IRQs within CPUMIPSState
Based-on: <20250121155526.29982-2-philmd@linaro.org>
"hw/irq: Introduce qemu_init_irqs() helper"
^ permalink raw reply [flat|nested] 12+ messages in thread