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[88.21.68.240]) by smtp.gmail.com with ESMTPSA id z189sm2165291wmc.25.2019.09.24.03.04.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Sep 2019 03:04:13 -0700 (PDT) Subject: Re: [PATCH 0/4] xics: Eliminate unnecessary class To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Greg Kurz References: <20190924045952.11412-1-david@gibson.dropbear.id.au> <20190924095200.7f624278@bahia.lan> <98e7128c-e305-ab7a-b138-da1c56266805@kaod.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <7ae8863e-0718-b18f-5d52-3c41d813b026@redhat.com> Date: Tue, 24 Sep 2019 12:04:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <98e7128c-e305-ab7a-b138-da1c56266805@kaod.org> Content-Language: en-US X-MC-Unique: lK_VLwVAOn2IG4Qzg2NkBw-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gkurz@kaod.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi C=C3=A9dric, On 9/24/19 11:55 AM, C=C3=A9dric Le Goater wrote: > On 24/09/2019 09:52, Greg Kurz wrote: >> On Tue, 24 Sep 2019 07:22:51 +0200 >> C=C3=A9dric Le Goater wrote: >> >>> On 24/09/2019 06:59, David Gibson wrote: >>>> The XICS interrupt controller device used to have separate subtypes >>>> for the KVM and non-KVM variant of the device. That was a bad idea, >>>> because it leaked information that should be entirely host-side >>>> implementation specific to the kinda-sorta guest visible QOM class >>>> names. >>>> >>>> We eliminated the KVM specific class some time ago, but it's left >>>> behind a distinction between the TYPE_ICS_BASE abstract class and >>>> TYPE_ICS_SIMPLE subtype which no longer serves any purpose. >>>> >>>> This series collapses the two types back into one. >>> >>> OK. Is it migration compatible ? because this is why we have kept >> >> Yeah, the types themselves don't matter, only the format of the >> binary stream described in the VMStateDescription does. >> >>> this subclass. I am glad we can remove it finally.=20 >>> >> >> I was thinking we were keeping that for pnv... >=20 >=20 > Yes, also. See the resend and reject handler in the code=20 > below. >=20 >=20 > I have been maintaining this patch since QEMU 2.6. I think=20 > it is time for me to declare defeat on getting it merged=20 > and QEMU 4.2 will be the last rebase.=20 Do you remember what is missing for being merged upstream? > /* > * QEMU PowerPC PowerNV PHB3 model > * > * Copyright (c) 2014-2018, IBM Corporation. > * > * This code is licensed under the GPL version 2 or later. See the > * COPYING file in the top-level directory. > */ > #include "qemu/osdep.h" > #include "qemu/log.h" > #include "qapi/error.h" > #include "qemu-common.h" > #include "hw/pci-host/pnv_phb3_regs.h" > #include "hw/pci-host/pnv_phb3.h" > #include "hw/ppc/pnv.h" > #include "hw/pci/msi.h" > #include "monitor/monitor.h" > #include "hw/irq.h" > #include "hw/qdev-properties.h" > #include "sysemu/reset.h" >=20 > static uint64_t phb3_msi_ive_addr(PnvPHB3 *phb, int srcno) > { > uint64_t ivtbar =3D phb->regs[PHB_IVT_BAR >> 3]; > uint64_t phbctl =3D phb->regs[PHB_CONTROL >> 3]; >=20 > if (!(ivtbar & PHB_IVT_BAR_ENABLE)) { > qemu_log_mask(LOG_GUEST_ERROR, "Failed access to disable IVT BAR = !"); > return 0; > } >=20 > if (srcno >=3D (ivtbar & PHB_IVT_LENGTH_MASK)) { > qemu_log_mask(LOG_GUEST_ERROR, "MSI out of bounds (%d vs 0x%"PRI= x64")", > srcno, (uint64_t) (ivtbar & PHB_IVT_LENGTH_MASK)); > return 0; > } >=20 > ivtbar &=3D PHB_IVT_BASE_ADDRESS_MASK; >=20 > if (phbctl & PHB_CTRL_IVE_128_BYTES) { > return ivtbar + 128 * srcno; > } else { > return ivtbar + 16 * srcno; > } > } >=20 > static bool phb3_msi_read_ive(PnvPHB3 *phb, int srcno, uint64_t *out_ive) > { > uint64_t ive_addr, ive; >=20 > ive_addr =3D phb3_msi_ive_addr(phb, srcno); > if (!ive_addr) { > return false; > } >=20 > if (dma_memory_read(&address_space_memory, ive_addr, &ive, sizeof(ive= ))) { > qemu_log_mask(LOG_GUEST_ERROR, "Failed to read IVE at 0x%" PRIx64= , > ive_addr); > return false; > } > *out_ive =3D be64_to_cpu(ive); >=20 > return true; > } >=20 > static void phb3_msi_set_p(Phb3MsiState *msi, int srcno, uint8_t gen) > { > uint64_t ive_addr; > uint8_t p =3D 0x01 | (gen << 1); >=20 > ive_addr =3D phb3_msi_ive_addr(msi->phb, srcno); > if (!ive_addr) { > return; > } >=20 > if (dma_memory_write(&address_space_memory, ive_addr + 4, &p, 1)) { > qemu_log_mask(LOG_GUEST_ERROR, > "Failed to write IVE (set P) at 0x%" PRIx64, ive_ad= dr); > } > } >=20 > static void phb3_msi_set_q(Phb3MsiState *msi, int srcno) > { > uint64_t ive_addr; > uint8_t q =3D 0x01; >=20 > ive_addr =3D phb3_msi_ive_addr(msi->phb, srcno); > if (!ive_addr) { > return; > } >=20 > if (dma_memory_write(&address_space_memory, ive_addr + 5, &q, 1)) { > qemu_log_mask(LOG_GUEST_ERROR, > "Failed to write IVE (set Q) at 0x%" PRIx64, ive_ad= dr); > } > } >=20 > static void phb3_msi_try_send(Phb3MsiState *msi, int srcno, bool force) > { > ICSState *ics =3D ICS_BASE(msi); > uint64_t ive; > uint64_t server, prio, pq, gen; >=20 > if (!phb3_msi_read_ive(msi->phb, srcno, &ive)) { > return; > } >=20 > server =3D GETFIELD(IODA2_IVT_SERVER, ive); > prio =3D GETFIELD(IODA2_IVT_PRIORITY, ive); > if (!force) { > pq =3D GETFIELD(IODA2_IVT_Q, ive) | (GETFIELD(IODA2_IVT_P, ive) <= < 1); > } else { > pq =3D 0; > } > gen =3D GETFIELD(IODA2_IVT_GEN, ive); >=20 > /* > * The low order 2 bits are the link pointer (Type II interrupts). > * Shift back to get a valid IRQ server. > */ > server >>=3D 2; >=20 > switch (pq) { > case 0: /* 00 */ > if (prio =3D=3D 0xff) { > /* Masked, set Q */ > phb3_msi_set_q(msi, srcno); > } else { > /* Enabled, set P and send */ > phb3_msi_set_p(msi, srcno, gen); > icp_irq(ics, server, srcno + ics->offset, prio); > } > break; > case 2: /* 10 */ > /* Already pending, set Q */ > phb3_msi_set_q(msi, srcno); > break; > case 1: /* 01 */ > case 3: /* 11 */ > default: > /* Just drop stuff if Q already set */ > break; > } > } >=20 > static void phb3_msi_set_irq(void *opaque, int srcno, int val) > { > Phb3MsiState *msi =3D PHB3_MSI(opaque); >=20 > if (val) { > phb3_msi_try_send(msi, srcno, false); > } > } >=20 >=20 > void pnv_phb3_msi_send(Phb3MsiState *msi, uint64_t addr, uint16_t data, > int32_t dev_pe) > { > ICSState *ics =3D ICS_BASE(msi); > uint64_t ive; > uint16_t pe; > uint32_t src =3D ((addr >> 4) & 0xffff) | (data & 0x1f); >=20 > if (src >=3D ics->nr_irqs) { > qemu_log_mask(LOG_GUEST_ERROR, "MSI %d out of bounds", src); > return; > } > if (dev_pe >=3D 0) { > if (!phb3_msi_read_ive(msi->phb, src, &ive)) { > return; > } > pe =3D GETFIELD(IODA2_IVT_PE, ive); > if (pe !=3D dev_pe) { > qemu_log_mask(LOG_GUEST_ERROR, > "MSI %d send by PE#%d but assigned to PE#%d", > src, dev_pe, pe); > return; > } > } > qemu_irq_pulse(msi->qirqs[src]); > } >=20 > void pnv_phb3_msi_ffi(Phb3MsiState *msi, uint64_t val) > { > /* Emit interrupt */ > pnv_phb3_msi_send(msi, val, 0, -1); >=20 > /* Clear FFI lock */ > msi->phb->regs[PHB_FFI_LOCK >> 3] =3D 0; > } >=20 > static void phb3_msi_reject(ICSState *ics, uint32_t nr) > { > Phb3MsiState *msi =3D PHB3_MSI(ics); > unsigned int srcno =3D nr - ics->offset; > unsigned int idx =3D srcno >> 6; > unsigned int bit =3D 1ull << (srcno & 0x3f); >=20 > assert(srcno < PHB3_MAX_MSI); >=20 > msi->rba[idx] |=3D bit; > msi->rba_sum |=3D (1u << idx); > } >=20 > static void phb3_msi_resend(ICSState *ics) > { > Phb3MsiState *msi =3D PHB3_MSI(ics); > unsigned int i, j; >=20 > if (msi->rba_sum =3D=3D 0) { > return; > } >=20 > for (i =3D 0; i < 32; i++) { > if ((msi->rba_sum & (1u << i)) =3D=3D 0) { > continue; > } > msi->rba_sum &=3D ~(1u << i); > for (j =3D 0; j < 64; j++) { > if ((msi->rba[i] & (1ull << j)) =3D=3D 0) { > continue; > } > msi->rba[i] &=3D ~(1u << j); > phb3_msi_try_send(msi, i * 64 + j, true); > } > } > } >=20 > static void phb3_msi_print_info(ICSState *ics, Monitor *mon) > { > Phb3MsiState *msi =3D PHB3_MSI(ics); > int i; >=20 > for (i =3D 0; i < ics->nr_irqs; i++) { > uint64_t ive; >=20 > if (!phb3_msi_read_ive(msi->phb, i, &ive)) { > return; > } >=20 > if (GETFIELD(IODA2_IVT_PRIORITY, ive) =3D=3D 0xff) { > continue; > } >=20 > monitor_printf(mon, " %4x %c%c server=3D%04x prio=3D%02x gen=3D%= d\n", > ics->offset + i, > GETFIELD(IODA2_IVT_P, ive) ? 'P' : '-', > GETFIELD(IODA2_IVT_Q, ive) ? 'Q' : '-', > (uint32_t) GETFIELD(IODA2_IVT_SERVER, ive) >> 2, > (uint32_t) GETFIELD(IODA2_IVT_PRIORITY, ive), > (uint32_t) GETFIELD(IODA2_IVT_GEN, ive)); > } > } >=20 > static void phb3_msi_reset(DeviceState *dev) > { > Phb3MsiState *msi =3D PHB3_MSI(dev); > ICSStateClass *icsc =3D ICS_BASE_GET_CLASS(dev); >=20 > icsc->parent_reset(dev); >=20 > memset(msi->rba, 0, sizeof(msi->rba)); > msi->rba_sum =3D 0; > } >=20 > static void phb3_msi_reset_handler(void *dev) > { > phb3_msi_reset(dev); > } >=20 > void pnv_phb3_msi_update_config(Phb3MsiState *msi, uint32_t base, > uint32_t count) > { > ICSState *ics =3D ICS_BASE(msi); >=20 > if (count > PHB3_MAX_MSI) { > count =3D PHB3_MAX_MSI; > } > ics->nr_irqs =3D count; > ics->offset =3D base; > } >=20 > static void phb3_msi_realize(DeviceState *dev, Error **errp) > { > Phb3MsiState *msi =3D PHB3_MSI(dev); > ICSState *ics =3D ICS_BASE(msi); > ICSStateClass *icsc =3D ICS_BASE_GET_CLASS(ics); > Object *obj; > Error *local_err =3D NULL; >=20 > icsc->parent_realize(dev, &local_err); > if (local_err) { > error_propagate(errp, local_err); > return; > } >=20 > obj =3D object_property_get_link(OBJECT(dev), "phb", &local_err); > if (!obj) { > error_propagate(errp, local_err); > error_prepend(errp, "required link 'phb' not found: "); > return; > } > msi->phb =3D PNV_PHB3(obj); >=20 > msi->qirqs =3D qemu_allocate_irqs(phb3_msi_set_irq, msi, ics->nr_irqs= ); >=20 > qemu_register_reset(phb3_msi_reset_handler, dev); > } >=20 > static void phb3_msi_instance_init(Object *obj) > { > ICSState *ics =3D ICS_BASE(obj); >=20 > /* Will be overriden later */ > ics->offset =3D 0; > } >=20 > static void phb3_msi_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > ICSStateClass *isc =3D ICS_BASE_CLASS(klass); >=20 > device_class_set_parent_realize(dc, phb3_msi_realize, > &isc->parent_realize); > device_class_set_parent_reset(dc, phb3_msi_reset, > &isc->parent_reset); >=20 > isc->reject =3D phb3_msi_reject; > isc->resend =3D phb3_msi_resend; > isc->print_info =3D phb3_msi_print_info; > } >=20 > static const TypeInfo phb3_msi_info =3D { > .name =3D TYPE_PHB3_MSI, > .parent =3D TYPE_ICS_BASE, > .instance_size =3D sizeof(Phb3MsiState), > .class_init =3D phb3_msi_class_init, > .class_size =3D sizeof(ICSStateClass), > .instance_init =3D phb3_msi_instance_init, > }; >=20 > static void pnv_phb3_msi_register_types(void) > { > type_register_static(&phb3_msi_info); > } >=20 > type_init(pnv_phb3_msi_register_types) >=20