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[92.88.171.187]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43661219578sm455641215e9.20.2025.01.02.04.20.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Jan 2025 04:20:59 -0800 (PST) Message-ID: <7b06d49b-33f1-42f1-8572-7c300e4ef3d9@linaro.org> Date: Thu, 2 Jan 2025 13:20:57 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/19] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Anton Johansson Cc: "Edgar E. Iglesias" , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= , Paolo Bonzini , Jason Wang , Richard Henderson References: <20241105130431.22564-1-philmd@linaro.org> <20241105130431.22564-8-philmd@linaro.org> <21b166ef-258c-4497-abf2-135022eb4f0e@linaro.org> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/11/24 23:27, Philippe Mathieu-Daudé wrote: > On 5/11/24 23:24, Philippe Mathieu-Daudé wrote: >> On 5/11/24 14:04, Philippe Mathieu-Daudé wrote: >>> All these MemoryRegionOps read() and write() handlers are >>> implemented expecting 32-bit accesses. Clarify that setting >>> .impl.min/max_access_size fields. >>> >>> Signed-off-by: Philippe Mathieu-Daudé >>> --- >>>   hw/char/xilinx_uartlite.c | 4 ++++ >>>   hw/intc/xilinx_intc.c     | 4 ++++ >>>   hw/net/xilinx_ethlite.c   | 4 ++++ >>>   hw/timer/xilinx_timer.c   | 4 ++++ >>>   4 files changed, 16 insertions(+) >>> >>> diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c >>> index a69ad769cc4..892efe81fee 100644 >>> --- a/hw/char/xilinx_uartlite.c >>> +++ b/hw/char/xilinx_uartlite.c >>> @@ -170,6 +170,10 @@ static const MemoryRegionOps uart_ops = { >>>       .read = uart_read, >>>       .write = uart_write, >>>       .endianness = DEVICE_NATIVE_ENDIAN, >>> +    .impl = { >>> +        .min_access_size = 4, > > Odd. The change makes the qtests pass, but here I'm modifying .impl, > not .valid... Since .valid.min_access_size = 1, SBI is a valid > opcode, no need to use SWI. Which proves this device is only mapped in little-endian. > >>> +        .max_access_size = 4, >>> +    }, >>>       .valid = { >>>           .min_access_size = 1, >>>           .max_access_size = 4, >> >> To have qtests working I need to squash: >> >> -- >8 -- >> diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial- >> test.c >> index 3b92fa5d506..6d9291c8ae2 100644 >> --- a/tests/qtest/boot-serial-test.c >> +++ b/tests/qtest/boot-serial-test.c >> @@ -57,7 +57,7 @@ static const uint8_t kernel_pls3adsp1800[] = { >>       0xb0, 0x00, 0x84, 0x00,                 /* imm   0x8400 */ >>       0x30, 0x60, 0x00, 0x04,                 /* addik r3,r0,4 */ >>       0x30, 0x80, 0x00, 0x54,                 /* addik r4,r0,'T' */ >> -    0xf0, 0x83, 0x00, 0x00,                 /* sbi   r4,r3,0 */ >> +    0xf8, 0x83, 0x00, 0x00,                 /* swi   r4,r3,0 */ >>       0xb8, 0x00, 0xff, 0xfc                  /* bri   -4  loop */ >>   }; >> >> @@ -65,7 +65,7 @@ static const uint8_t kernel_plml605[] = { >>       0xe0, 0x83, 0x00, 0xb0,                 /* imm   0x83e0 */ >>       0x00, 0x10, 0x60, 0x30,                 /* addik r3,r0,0x1000 */ >>       0x54, 0x00, 0x80, 0x30,                 /* addik r4,r0,'T' */ >> -    0x00, 0x00, 0x83, 0xf0,                 /* sbi   r4,r3,0 */ >> +    0x00, 0x00, 0x83, 0xf8,                 /* swi   r4,r3,0 */ >>       0xfc, 0xff, 0x00, 0xb8                  /* bri   -4  loop */ >>   }; >> --- >> >> to access the uart by 32-bit instead of 8-bit.