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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7246a9d40a2sm1519807b3a.193.2024.11.14.09.57.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Nov 2024 09:57:00 -0800 (PST) Message-ID: <7b0e0cb8-0f71-43a4-b503-ab4e2298a561@linaro.org> Date: Thu, 14 Nov 2024 09:56:59 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 07/54] accel/tcg: Assert bits in range in tlb_flush_range_by_mmuidx* Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20241114160131.48616-1-richard.henderson@linaro.org> <20241114160131.48616-8-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20241114160131.48616-8-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/14/24 08:00, Richard Henderson wrote: > The only target that does not use TARGET_LONG_BITS is Arm, which > only reduces bits based on TBI. There is no point in handling > odd combinations of parameters. > > Signed-off-by: Richard Henderson > --- > accel/tcg/cputlb.c | 16 ++++------------ > 1 file changed, 4 insertions(+), 12 deletions(-) > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index 1346a26d90..5510f40333 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -792,20 +792,16 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, > > assert_cpu_is_self(cpu); > assert(len != 0); > + assert(bits > TARGET_PAGE_BITS && bits <= TARGET_LONG_BITS); > > /* > * If all bits are significant, and len is small, > * this devolves to tlb_flush_page. > */ > - if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { > + if (bits == TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { > tlb_flush_page_by_mmuidx(cpu, addr, idxmap); > return; > } > - /* If no page bits are significant, this devolves to tlb_flush. */ > - if (bits < TARGET_PAGE_BITS) { > - tlb_flush_by_mmuidx(cpu, idxmap); > - return; > - } > > /* This should already be page aligned */ > d.addr = addr & TARGET_PAGE_MASK; > @@ -832,20 +828,16 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, > CPUState *dst_cpu; > > assert(len != 0); > + assert(bits > TARGET_PAGE_BITS && bits <= TARGET_LONG_BITS); > > /* > * If all bits are significant, and len is small, > * this devolves to tlb_flush_page. > */ > - if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { > + if (bits == TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) { > tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); > return; > } > - /* If no page bits are significant, this devolves to tlb_flush. */ > - if (bits < TARGET_PAGE_BITS) { > - tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, idxmap); > - return; > - } > > /* This should already be page aligned */ > d.addr = addr & TARGET_PAGE_MASK; Reviewed-by: Pierrick Bouvier