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[93.34.153.63]) by smtp.gmail.com with ESMTPSA id n3sm17634818wro.59.2019.06.26.11.42.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 11:42:21 -0700 (PDT) To: Mark Cave-Ayland , Aleksandar Markovic References: <20190519041522.12327-1-richard.henderson@linaro.org> <8f28d008-2608-a579-7505-4546b08deb41@linaro.org> <085d6881-f518-9888-a13e-081cdc09de46@ilande.co.uk> <0b9f4772-37f6-1453-e4ea-5ad9d0f52a5b@ilande.co.uk> <68facefc-b801-4902-11c0-4542662bfc4e@linaro.org> <16f26b7f-2435-aa05-66a3-073e8310d5c8@linaro.org> <0ceec012-fcdc-ccde-291a-121a4e475f86@ilande.co.uk> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <7b1699e1-28ca-a58f-787e-c0ca11666b90@linaro.org> Date: Wed, 26 Jun 2019 20:42:19 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <0ceec012-fcdc-ccde-291a-121a4e475f86@ilande.co.uk> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: Re: [Qemu-devel] [PATCH v4 0/7] tcg/ppc: Add vector opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Howard Spoelstra , QEMU Developers , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/26/19 7:00 PM, Mark Cave-Ayland wrote: > Interestingly if I set a trap and then switch the opcode to "lis r4,0" (0x3c800000) > then we carry on as normal until the next "lis r2,0" instruction. Looking through the > whole output of -d out_asm this is the first mention of r2 which makes me wonder if > it is special somehow? At least a quick search indicates that for 32-bit PPC r2 is > supposed to be dedicated as a TOC pointer. > > Is there a quick way to disable r2 from the list of available registers to see if > that gets things going? Interesting. I'm not sure why that's happening. As a quick hack, /* For some memory operations, we need a scratch that isn't R0. For the AIX calling convention, we can re-use the TOC register since we'll be reloading it at every call. Otherwise R12 will do nicely as neither a call-saved register nor a parameter register. */ - #ifdef _CALL_AIX + #if 0 # define TCG_REG_TMP1 TCG_REG_R2 #else # define TCG_REG_TMP1 TCG_REG_R12 #endif But I thought that _CALL_AIX was only defined for ppc64 elf version 1. I thought that ppc32 used _CALL_SYSV instead. Certainly that's what is used elsewhere... r~